##// END OF EJS Templates
Many corrections, mainly related to 807 Don_Enumeration
paul -
r318:d3701d39af11 R3_plus draft
parent child
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@@ -1,2 +1,2
1 1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
2 3e4216a0e6981bead8bcb201012ebadb53f60dff header/lfr_common_headers
2 6bab694410c69700e3455ffba21ce58dbb4da870 header/lfr_common_headers
@@ -10,6 +10,30
10 10 #include "fsw_spacewire.h"
11 11 #include "lfr_cpu_usage_report.h"
12 12
13 #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0
14 #define WATCHDOG_LOOP_PRINTF 10
15 #define WATCHDOG_LOOP_DEBUG 3
16
17 #define DUMB_MESSAGE_NB 15
18 #define NB_RTEMS_EVENTS 32
19 #define EVENT_12 12
20 #define EVENT_13 13
21 #define EVENT_14 14
22 #define DUMB_MESSAGE_0 "in DUMB *** default"
23 #define DUMB_MESSAGE_1 "in DUMB *** timecode_irq_handler"
24 #define DUMB_MESSAGE_2 "in DUMB *** f3 buffer changed"
25 #define DUMB_MESSAGE_3 "in DUMB *** in SMIQ *** Error sending event to AVF0"
26 #define DUMB_MESSAGE_4 "in DUMB *** spectral_matrices_isr *** Error sending event to SMIQ"
27 #define DUMB_MESSAGE_5 "in DUMB *** waveforms_simulator_isr"
28 #define DUMB_MESSAGE_6 "VHDL SM *** two buffers f0 ready"
29 #define DUMB_MESSAGE_7 "ready for dump"
30 #define DUMB_MESSAGE_8 "VHDL ERR *** spectral matrix"
31 #define DUMB_MESSAGE_9 "tick"
32 #define DUMB_MESSAGE_10 "VHDL ERR *** waveform picker"
33 #define DUMB_MESSAGE_11 "VHDL ERR *** unexpected ready matrix values"
34 #define DUMB_MESSAGE_12 "WATCHDOG timer"
35 #define DUMB_MESSAGE_13 "TIMECODE timer"
36 #define DUMB_MESSAGE_14 "TIMECODE ISR"
13 37
14 38 enum lfr_reset_cause_t{
15 39 UNKNOWN_CAUSE,
@@ -46,8 +70,6 extern gptimer_regs_t *gptimer_regs;
46 70 extern void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int*, unsigned int* );
47 71 extern void CCR_getInstructionAndDataErrorCounters( unsigned int*, unsigned int* );
48 72
49 #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0
50
51 73 rtems_name name_hk_rate_monotonic; // name of the HK rate monotonic
52 74 rtems_id HK_id; // id of the HK rate monotonic period
53 75 rtems_name name_avgv_rate_monotonic; // name of the AVGV rate monotonic
@@ -13,6 +13,15
13 13 #include "tc_handler.h"
14 14 #include "fsw_init.h"
15 15
16 #define SPW_LINK_OK 5
17 #define CONF_TCODE_CTRL 0x0909 // [Time Rx : Time Tx : Link error : Tick-out IRQ]
18 #define SPW_BIT_NP 0x00100000 // [NP] set the No port force bit
19 #define SPW_BIT_NP_MASK 0xffdfffff
20 #define SPW_BIT_RE 0x00010000 // [RE] set the RMAP Enable bit
21 #define SPW_BIT_RE_MASK 0xfffdffff
22 #define SPW_LINK_STAT_POS 21
23 #define SPW_TIMECODE_MAX 63
24
16 25 extern spw_stats grspw_stats;
17 26 extern rtems_name timecode_timer_name;
18 27 extern rtems_id timecode_timer_id;
@@ -30,6 +30,18 typedef struct {
30 30 volatile unsigned int unused;
31 31 } timer_regs_t;
32 32
33 //*************
34 //*************
35 // GPTIMER_REGS
36
37 #define GPTIMER_CLEAR_IRQ 0x00000010 // clear pending IRQ if any
38 #define GPTIMER_LD 0x00000004 // LD load value from the reload register
39 #define GPTIMER_EN 0x00000001 // EN enable the timer
40 #define GPTIMER_EN_MASK 0xfffffffe // EN enable the timer
41 #define GPTIMER_RS 0x00000002 // RS restart
42 #define GPTIMER_IE 0x00000008 // IE interrupt enable
43 #define GPTIMER_IE_MASK 0xffffffef // IE interrupt enable
44
33 45 typedef struct {
34 46 volatile unsigned int scaler_value;
35 47 volatile unsigned int scaler_reload;
@@ -38,6 +50,25 typedef struct {
38 50 timer_regs_t timer[NB_GPTIMER];
39 51 } gptimer_regs_t;
40 52
53 //*********************
54 //*********************
55 // TIME_MANAGEMENT_REGS
56
57 #define VAL_SOFTWARE_RESET 0x02 // [0010] software reset
58 #define VAL_LFR_SYNCHRONIZED 0x80000000
59 #define BIT_SYNCHRONIZATION 31
60 #define COARSE_TIME_MASK 0x7fffffff
61 #define SYNC_BIT_MASK 0x7f
62 #define SYNC_BIT 0x80
63 #define BIT_CAL_RELOAD 0x00000010
64 #define MASK_CAL_RELOAD 0xffffffef // [1110 1111]
65 #define BIT_CAL_ENABLE 0x00000040
66 #define MASK_CAL_ENABLE 0xffffffbf // [1011 1111]
67 #define BIT_SET_INTERLEAVED 0x00000020 // [0010 0000]
68 #define MASK_SET_INTERLEAVED 0xffffffdf // [1101 1111]
69 #define BIT_SOFT_RESET 0x00000004 // [0100]
70 #define MASK_SOFT_RESET 0xfffffffb // [1011]
71
41 72 typedef struct {
42 73 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
43 74 // bit 1 is the soft reset for the time management module
@@ -57,6 +88,45 typedef struct {
57 88 volatile unsigned int calData;
58 89 } time_management_regs_t;
59 90
91 //*********************
92 //*********************
93 // WAVEFORM_PICKER_REGS
94
95 #define BITS_WFP_STATUS_F3 0xc0 // [1100 0000] check the f3 full bits
96 #define BIT_WFP_BUF_F3_0 0x40 // [0100 0000] f3 buffer 0 is full
97 #define BIT_WFP_BUF_F3_1 0x80 // [1000 0000] f3 buffer 1 is full
98 #define RST_WFP_F3_0 0x00008840 // [1000 1000 0100 0000]
99 #define RST_WFP_F3_1 0x00008880 // [1000 1000 1000 0000]
100
101 #define BITS_WFP_STATUS_F2 0x30 // [0011 0000] get the status bits for f2
102 #define SHIFT_WFP_STATUS_F2 4
103 #define BIT_WFP_BUF_F2_0 0x10 // [0001 0000] f2 buffer 0 is full
104 #define BIT_WFP_BUF_F2_1 0x20 // [0010 0000] f2 buffer 1 is full
105 #define RST_WFP_F2_0 0x00004410 // [0100 0100 0001 0000]
106 #define RST_WFP_F2_1 0x00004420 // [0100 0100 0010 0000]
107
108 #define BITS_WFP_STATUS_F1 0x0c // [0000 1100] check the f1 full bits
109 #define BIT_WFP_BUF_F1_0 0x04 // [0000 0100] f1 buffer 0 is full
110 #define BIT_WFP_BUF_F1_1 0x08 // [0000 1000] f1 buffer 1 is full
111 #define RST_WFP_F1_0 0x00002204 // [0010 0010 0000 0100] f1 bits = 0
112 #define RST_WFP_F1_1 0x00002208 // [0010 0010 0000 1000] f1 bits = 0
113
114 #define BITS_WFP_STATUS_F0 0x03 // [0000 0011] check the f0 full bits
115 #define RST_WFP_F0_0 0x00001101 // [0001 0001 0000 0001]
116 #define RST_WFP_F0_1 0x00001102 // [0001 0001 0000 0010]
117
118 #define BIT_WFP_BUFFER_0 0x01
119 #define BIT_WFP_BUFFER_1 0x02
120
121 #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0
122 #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst
123 #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled
124
125 #define DFLT_WFP_NB_DATA_BY_BUFFER 0xa7f // 0x30 *** 2688 - 1 => nb samples -1
126 #define DFLT_WFP_SNAPSHOT_PARAM 0xa80 // 0x34 *** 2688 => nb samples
127 #define DFLT_WFP_BUFFER_LENGTH 0x1f8 // buffer length in burst = 3 * 2688 / 16 = 504 = 0x1f8
128 #define DFLT_WFP_DELTA_F0_2 0x30 // 48 = 11 0000, max 7 bits
129
60 130 // PDB >= 0.1.28, 0x80000f54
61 131 typedef struct{
62 132 int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW
@@ -106,6 +176,29 typedef struct{
106 176 volatile unsigned int e2; // 0x98
107 177 } waveform_picker_regs_0_1_18_t;
108 178
179 //*********************
180 //*********************
181 // SPECTRAL_MATRIX_REGS
182
183 #define BITS_STATUS_F0 0x03 // [0011]
184 #define BITS_STATUS_F1 0x0c // [1100]
185 #define BITS_STATUS_F2 0x30 // [0011 0000]
186 #define BITS_HK_AA_SM 0x780 // [0111 1000 0000]
187 #define BITS_SM_ERR 0x7c0 // [0111 1100 0000]
188 #define BITS_STATUS_REG 0x7ff // [0111 1111 1111]
189 #define BIT_READY_0 0x1 // [01]
190 #define BIT_READY_1 0x2 // [10]
191 #define BIT_READY_0_1 0x3 // [11]
192 #define BIT_STATUS_F1_0 0x04 // [0100]
193 #define BIT_STATUS_F1_1 0x08 // [1000]
194 #define BIT_STATUS_F2_0 0x10 // [0001 0000]
195 #define BIT_STATUS_F2_1 0x20 // [0010 0000]
196 #define DEFAULT_MATRIX_LENGTH 0xc8 // 25 * 128 / 16 = 200 = 0xc8
197 #define BIT_IRQ_ON_NEW_MATRIX 0x01
198 #define MASK_IRQ_ON_NEW_MATRIX 0xfffffffe
199 #define BIT_IRQ_ON_ERROR 0x02
200 #define MASK_IRQ_ON_ERROR 0xfffffffd
201
109 202 typedef struct {
110 203 volatile int config; // 0x00
111 204 volatile int status; // 0x04
@@ -29,4 +29,8
29 29
30 30 unsigned char lfr_rtems_cpu_usage_report( void );
31 31
32 #define CONST_100 100
33 #define CONST_1000 1000
34 #define CONST_100000 100000
35
32 36 #endif // LFR_CPU_USAGE_REPORT_H
@@ -11,6 +11,10
11 11
12 12 #include "fsw_params.h"
13 13
14 #define SBM_COEFF_PER_NORM_COEFF 2
15 #define MAX_SRC_DATA 780 // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
16 #define MAX_SRC_DATA_WITH_SPARE 143 // 13 bins * 11 Bytes
17
14 18 typedef struct ring_node_asm
15 19 {
16 20 struct ring_node_asm *next;
@@ -24,24 +28,24 typedef struct
24 28 unsigned char protocolIdentifier;
25 29 unsigned char reserved;
26 30 unsigned char userApplication;
27 unsigned char packetID[2];
28 unsigned char packetSequenceControl[2];
29 unsigned char packetLength[2];
31 unsigned char packetID[BYTES_PER_PACKETID];
32 unsigned char packetSequenceControl[BYTES_PER_SEQ_CTRL];
33 unsigned char packetLength[BYTES_PER_PKT_LEN];
30 34 // DATA FIELD HEADER
31 35 unsigned char spare1_pusVersion_spare2;
32 36 unsigned char serviceType;
33 37 unsigned char serviceSubType;
34 38 unsigned char destinationID;
35 unsigned char time[6];
39 unsigned char time[BYTES_PER_TIME];
36 40 // AUXILIARY HEADER
37 41 unsigned char sid;
38 42 unsigned char pa_bia_status_info;
39 43 unsigned char sy_lfr_common_parameters_spare;
40 44 unsigned char sy_lfr_common_parameters;
41 unsigned char acquisitionTime[6];
42 unsigned char pa_lfr_bp_blk_nr[2];
45 unsigned char acquisitionTime[BYTES_PER_TIME];
46 unsigned char pa_lfr_bp_blk_nr[BYTES_PER_BLKNR];
43 47 // SOURCE DATA
44 unsigned char data[ 780 ]; // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
48 unsigned char data[ MAX_SRC_DATA ]; // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
45 49 } bp_packet;
46 50
47 51 typedef struct
@@ -50,25 +54,25 typedef struct
50 54 unsigned char protocolIdentifier;
51 55 unsigned char reserved;
52 56 unsigned char userApplication;
53 unsigned char packetID[2];
54 unsigned char packetSequenceControl[2];
55 unsigned char packetLength[2];
57 unsigned char packetID[BYTES_PER_PACKETID];
58 unsigned char packetSequenceControl[BYTES_PER_SEQ_CTRL];
59 unsigned char packetLength[BYTES_PER_PKT_LEN];
56 60 // DATA FIELD HEADER
57 61 unsigned char spare1_pusVersion_spare2;
58 62 unsigned char serviceType;
59 63 unsigned char serviceSubType;
60 64 unsigned char destinationID;
61 unsigned char time[6];
65 unsigned char time[BYTES_PER_TIME];
62 66 // AUXILIARY HEADER
63 67 unsigned char sid;
64 68 unsigned char pa_bia_status_info;
65 69 unsigned char sy_lfr_common_parameters_spare;
66 70 unsigned char sy_lfr_common_parameters;
67 unsigned char acquisitionTime[6];
71 unsigned char acquisitionTime[BYTES_PER_TIME];
68 72 unsigned char source_data_spare;
69 unsigned char pa_lfr_bp_blk_nr[2];
73 unsigned char pa_lfr_bp_blk_nr[BYTES_PER_BLKNR];
70 74 // SOURCE DATA
71 unsigned char data[ 143 ]; // 13 bins * 11 Bytes
75 unsigned char data[ MAX_SRC_DATA_WITH_SPARE ]; // 13 bins * 11 Bytes
72 76 } bp_packet_with_spare; // only for TM_LFR_SCIENCE_NORMAL_BP1_F0 and F1
73 77
74 78 typedef struct asm_msg
@@ -99,8 +103,8 extern Packet_TM_LFR_PARAMETER_DUMP_t pa
99 103 extern time_management_regs_t *time_management_regs;
100 104 extern volatile spectral_matrix_regs_t *spectral_matrix_regs;
101 105
102 extern rtems_name misc_name[5];
103 extern rtems_id Task_id[20]; /* array of task ids */
106 extern rtems_name misc_name[];
107 extern rtems_id Task_id[]; /* array of task ids */
104 108
105 109 ring_node * getRingNodeForAveraging( unsigned char frequencyChannel);
106 110 // ISR
@@ -173,7 +177,7 void SM_average( float *averaged_spec_ma
173 177 float sum;
174 178 unsigned int i;
175 179 unsigned int k;
176 unsigned char incomingSMIsValid[8];
180 unsigned char incomingSMIsValid[NB_SM_BEFORE_AVF0_F1];
177 181 unsigned int numberOfValidSM;
178 182 unsigned char isValid;
179 183
@@ -181,7 +185,7 void SM_average( float *averaged_spec_ma
181 185 // PAS FILTERING
182 186 // check acquisitionTime of the incoming data
183 187 numberOfValidSM = 0;
184 for (k=0; k<8; k++)
188 for (k=0; k<NB_SM_BEFORE_AVF0_F1; k++)
185 189 {
186 190 isValid = acquisitionTimeIsValid( ring_node_tab[k]->coarseTime, ring_node_tab[k]->fineTime, channel );
187 191 incomingSMIsValid[k] = isValid;
@@ -201,14 +205,14 void SM_average( float *averaged_spec_ma
201 205 // + ( (int *) (ring_node_tab[6]->buffer_address) ) [ i ]
202 206 // + ( (int *) (ring_node_tab[7]->buffer_address) ) [ i ];
203 207
204 sum = ( (incomingSMIsValid[0] == 1) ? ( (int *) (ring_node_tab[0]->buffer_address) ) [ i ] : 0.0 )
205 + ( (incomingSMIsValid[1] == 1) ? ( (int *) (ring_node_tab[1]->buffer_address) ) [ i ] : 0.0 )
206 + ( (incomingSMIsValid[2] == 1) ? ( (int *) (ring_node_tab[2]->buffer_address) ) [ i ] : 0.0 )
207 + ( (incomingSMIsValid[3] == 1) ? ( (int *) (ring_node_tab[3]->buffer_address) ) [ i ] : 0.0 )
208 + ( (incomingSMIsValid[4] == 1) ? ( (int *) (ring_node_tab[4]->buffer_address) ) [ i ] : 0.0 )
209 + ( (incomingSMIsValid[5] == 1) ? ( (int *) (ring_node_tab[5]->buffer_address) ) [ i ] : 0.0 )
210 + ( (incomingSMIsValid[6] == 1) ? ( (int *) (ring_node_tab[6]->buffer_address) ) [ i ] : 0.0 )
211 + ( (incomingSMIsValid[7] == 1) ? ( (int *) (ring_node_tab[7]->buffer_address) ) [ i ] : 0.0 );
208 sum = ( incomingSMIsValid[0] * ((int *)(ring_node_tab[0]->buffer_address) )[ i ] )
209 + ( incomingSMIsValid[1] * ((int *)(ring_node_tab[1]->buffer_address) )[ i ] )
210 + ( incomingSMIsValid[2] * ((int *)(ring_node_tab[2]->buffer_address) )[ i ] )
211 + ( incomingSMIsValid[3] * ((int *)(ring_node_tab[3]->buffer_address) )[ i ] )
212 + ( incomingSMIsValid[4] * ((int *)(ring_node_tab[4]->buffer_address) )[ i ] )
213 + ( incomingSMIsValid[5] * ((int *)(ring_node_tab[5]->buffer_address) )[ i ] )
214 + ( incomingSMIsValid[6] * ((int *)(ring_node_tab[6]->buffer_address) )[ i ] )
215 + ( incomingSMIsValid[7] * ((int *)(ring_node_tab[7]->buffer_address) )[ i ] );
212 216
213 217 if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) )
214 218 {
@@ -278,13 +282,19 void ASM_reorganize_and_divide( float *a
278 282 for( frequencyBin = 0; frequencyBin < NB_BINS_PER_SM; frequencyBin++ )
279 283 {
280 284 offsetASMReorganized =
281 frequencyBin * NB_VALUES_PER_SM
285 (frequencyBin * NB_VALUES_PER_SM)
282 286 + asmComponent;
283 287 offsetASM =
284 asmComponent * NB_BINS_PER_SM
288 (asmComponent * NB_BINS_PER_SM)
285 289 + frequencyBin;
286 averaged_spec_mat_reorganized[offsetASMReorganized ] =
287 (divider != 0.0) ? averaged_spec_mat[ offsetASM ] / divider : 0.0;
290 if ( divider != INIT_FLOAT )
291 {
292 averaged_spec_mat_reorganized[offsetASMReorganized ] = averaged_spec_mat[ offsetASM ] / divider;
293 }
294 else
295 {
296 averaged_spec_mat_reorganized[offsetASMReorganized ] = INIT_FLOAT;
297 }
288 298 }
289 299 }
290 300 }
@@ -304,12 +314,12 void ASM_compress_reorganize_and_divide(
304 314 for( frequencyBin = 0; frequencyBin < nbBinsCompressedMatrix; frequencyBin++ )
305 315 {
306 316 offsetCompressed = // NO TIME OFFSET
307 frequencyBin * NB_VALUES_PER_SM
317 (frequencyBin * NB_VALUES_PER_SM)
308 318 + asmComponent;
309 319 offsetASM = // NO TIME OFFSET
310 asmComponent * NB_BINS_PER_SM
320 (asmComponent * NB_BINS_PER_SM)
311 321 + ASMIndexStart
312 + frequencyBin * nbBinsToAverage;
322 + (frequencyBin * nbBinsToAverage);
313 323 compressed_spec_mat[ offsetCompressed ] = 0;
314 324 for ( k = 0; k < nbBinsToAverage; k++ )
315 325 {
@@ -340,8 +350,8 void ASM_convert( volatile float *input_
340 350 {
341 351 for ( asmComponent=0; asmComponent<NB_VALUES_PER_SM; asmComponent++)
342 352 {
343 offsetInput = (frequencyBin*NB_VALUES_PER_SM) + asmComponent ;
344 offsetOutput = 2 * ( (frequencyBin*NB_VALUES_PER_SM) + asmComponent ) ;
353 offsetInput = (frequencyBin*NB_VALUES_PER_SM) + asmComponent ;
354 offsetOutput = SM_BYTES_PER_VAL * ( (frequencyBin*NB_VALUES_PER_SM) + asmComponent ) ;
345 355 pt_char_input = (char*) &input_matrix [ offsetInput ];
346 356 pt_char_output = (char*) &output_matrix[ offsetOutput ];
347 357 pt_char_output[0] = pt_char_input[0]; // bits 31 downto 24 of the float
@@ -1,9 +1,28
1 1 #ifndef TC_ACCEPTANCE_H_INCLUDED
2 2 #define TC_ACCEPTANCE_H_INCLUDED
3 3
4 //#include "tm_lfr_tc_exe.h"
5 4 #include "fsw_params.h"
6 5
6 #define BIT_0 0x01
7 #define BIT_1 0x02
8 #define BIT_2 0x04
9 #define BIT_3 0x08
10 #define BIT_4 0x10
11 #define BIT_5 0x20
12 #define BIT_6 0x40
13 #define BIT_7 0x80
14
15 #define CONST_CRC_0 0x1021
16 #define CONST_CRC_1 0x2042
17 #define CONST_CRC_2 0x4084
18 #define CONST_CRC_3 0x8108
19 #define CONST_CRC_4 0x1231
20 #define CONST_CRC_5 0x2462
21 #define CONST_CRC_6 0x48c4
22 #define CONST_CRC_7 0x9188
23
24 #define CRC_RESET 0xffff
25
7 26 //**********************
8 27 // GENERAL USE FUNCTIONS
9 28 unsigned int Crc_opt( unsigned char D, unsigned int Chk);
@@ -12,6 +12,36
12 12
13 13 #include "lfr_cpu_usage_report.h"
14 14
15 #define MAX_DELTA_COARSE_TIME 3
16 #define NB_SCIENCE_TASKS 10
17 #define NB_ASM_TASKS 6
18 #define STATUS_0 0
19 #define STATUS_1 1
20 #define STATUS_2 2
21 #define STATUS_3 3
22 #define STATUS_4 4
23 #define STATUS_5 5
24 #define STATUS_6 6
25 #define STATUS_7 7
26 #define STATUS_8 8
27 #define STATUS_9 9
28
29 #define CAL_F0 625
30 #define CAL_F1 10000
31 #define CAL_FS 160256.410
32 #define CAL_SCALE_FACTOR (0.250 / 0.000654) // 191, 500 mVpp, 2 sinus waves => 500 mVpp each, amplitude = 250 mV
33 #define CAL_NB_PTS 256
34 #define CAL_DATA_MASK 0xfff
35 #define CAL_F_DIVISOR 38 // 25 MHz => 160 256 (39 - 1)
36 // INTERLEAVED MODE
37 #define CAL_FS_INTER 240384.615
38 #define CAL_NB_PTS_INTER 384
39 #define CAL_DATA_MASK_INTER 0x3f
40 #define CAL_DATA_SHIFT_INTER 12
41 #define BYTES_FOR_2_SAMPLES 3 // one need 3 bytes = 24 bits to store 3 samples of 12 bits in interleaved mode
42 #define STEPS_FOR_STORAGE_INTER 128
43 #define CAL_F_DIVISOR_INTER 26 // 25 MHz => 240 384
44
15 45 extern unsigned int lastValidEnterModeTime;
16 46 extern unsigned char oneTcLfrUpdateTimeReceived;
17 47
@@ -11,7 +11,25
11 11 #include "basic_parameters_params.h"
12 12 #include "avf0_prc0.h"
13 13
14 #define FLOAT_EQUAL_ZERO 0.001
14 #define FLOAT_EQUAL_ZERO 0.001
15 #define NB_BINS_TO_REMOVE 3
16 #define FI_INTERVAL_COEFF 0.285
17 #define BIN_MIN 0
18 #define BIN_MAX 127
19 #define DELTAF_F0 96.
20 #define DELTAF_F1 16.
21 #define DELTAF_F2 1.
22
23 #define BIT_RW1_F1 0x80
24 #define BIT_RW1_F2 0x40
25 #define BIT_RW2_F1 0x20
26 #define BIT_RW2_F2 0x10
27 #define BIT_RW3_F1 0x08
28 #define BIT_RW3_F2 0x04
29 #define BIT_RW4_F1 0x02
30 #define BIT_RW4_F2 0x01
31
32 #define SBM_KCOEFF_PER_NORM_KCOEFF 2
15 33
16 34 extern unsigned short sequenceCounterParameterDump;
17 35 extern unsigned short sequenceCounters_TM_DUMP[];
@@ -11,6 +11,33
11 11 #include "fsw_params_wf_handler.h"
12 12
13 13 #define pi 3.14159265359
14 #define T0_IN_FINETIME ( 65536. / 24576. )
15 #define T1_IN_FINETIME ( 65536. / 4096. )
16 #define T2_IN_FINETIME ( 65536. / 256. )
17 #define T3_IN_FINETIME ( 65536. / 16. )
18
19 #define TICKS_PER_T1 16
20 #define TICKS_PER_T2 256
21 #define TICKS_PER_S 65536.
22 #define MS_PER_S 1000.
23
24 #define FREQ_F0 24576.
25 #define FREQ_F1 4096.
26 #define FREQ_F2 256.
27 #define FREQ_F3 16.
28
29 #define DELTAT_F0 2731 // (2048. / 24576. / 2.) * 65536. = 2730.667;
30 #define DELTAT_F1 16384 // (2048. / 4096. / 2.) * 65536. = 16384;
31 #define DELTAT_F2 262144 // (2048. / 256. / 2.) * 65536. = 262144;
32
33 #define OFFSET_2_BYTES 2
34
35 #define ONE_TICK_CORR_INTERVAL_0_MIN 0.5
36 #define ONE_TICK_CORR_INTERVAL_0_MAX 1.0
37 #define ONE_TICK_CORR_INTERVAL_1_MIN -1.0
38 #define ONE_TICK_CORR_INTERVAL_1_MAX -0.5
39 #define ONE_TICK_CORR 1
40 #define CORR_MULT 2
14 41
15 42 extern int fdSPW;
16 43
@@ -30,7 +57,7 extern struct param_local_str param_loca
30 57 extern unsigned short sequenceCounters_SCIENCE_NORMAL_BURST;
31 58 extern unsigned short sequenceCounters_SCIENCE_SBM1_SBM2;
32 59
33 extern rtems_id Task_id[20]; /* array of task ids */
60 extern rtems_id Task_id[]; /* array of task ids */
34 61
35 62 extern unsigned char lfrCurrentMode;
36 63
@@ -1,15 +1,16
1 1 #include <drvmgr/ambapp_bus.h>
2 2 #include <drvmgr/drvmgr.h>
3 #include <ccsds_types.h>
3 4
4 5 // GRSPW0 resources
5 6 struct drvmgr_key grlib_grspw_0n1_res[] =
6 7 {
7 {"txBdCnt", KEY_TYPE_INT, {(unsigned int)50}}, // 7 SWF_F0, 7 SWF_F1, 7 SWF_F2, 7 CWF_F3, 7 CWF_F1 ou 7 CWF_F2
8 {"rxBdCnt", KEY_TYPE_INT, {(unsigned int)10}},
9 {"txDataSize", KEY_TYPE_INT, {(unsigned int)4096}},
10 {"txHdrSize", KEY_TYPE_INT, {(unsigned int)34}},
11 {"rxPktSize", KEY_TYPE_INT, {(unsigned int)200}},
12 KEY_EMPTY
8 {"txBdCnt", KEY_TYPE_INT, {(unsigned int)TXBDCNT}}, // 7 SWF_F0, 7 SWF_F1, 7 SWF_F2, 7 CWF_F3, 7 CWF_F1 ou 7 CWF_F2
9 {"rxBdCnt", KEY_TYPE_INT, {(unsigned int)RXBDCNT}},
10 {"txDataSize", KEY_TYPE_INT, {(unsigned int)TXDATASIZE}},
11 {"txHdrSize", KEY_TYPE_INT, {(unsigned int)TXHDRSIZE}},
12 {"rxPktSize", KEY_TYPE_INT, {(unsigned int)RXPKTSIZE}},
13 KEY_EMPTY
13 14 };
14 15
15 16 // If RTEMS_DRVMGR_STARTUP is defined we override the "weak defaults" that is defined by the LEON3 BSP.
@@ -22,10 +22,13
22 22 #include "fsw_params.h"
23 23 #include "fsw_params_wf_handler.h"
24 24
25 #define NB_OF_TASKS 20
26 #define NB_OF_MISC_NAMES 5
27
25 28 // RTEMS GLOBAL VARIABLES
26 rtems_name misc_name[5];
27 rtems_name Task_name[20]; /* array of task names */
28 rtems_id Task_id[20]; /* array of task ids */
29 rtems_name misc_name[NB_OF_MISC_NAMES];
30 rtems_name Task_name[NB_OF_TASKS]; /* array of task names */
31 rtems_id Task_id[NB_OF_TASKS]; /* array of task ids */
29 32 rtems_name timecode_timer_name;
30 33 rtems_id timecode_timer_id;
31 34 int fdSPW = 0;
@@ -95,4 +98,5 float cp_rpw_sc_rw4_f2;
95 98 filterPar_t filterPar;
96 99
97 100 fbins_masks_t fbins_masks;
98 unsigned int acquisitionDurations[3] = {ACQUISITION_DURATION_F0, ACQUISITION_DURATION_F1, ACQUISITION_DURATION_F2};
101 unsigned int acquisitionDurations[NB_ACQUISITION_DURATION]
102 = {ACQUISITION_DURATION_F0, ACQUISITION_DURATION_F1, ACQUISITION_DURATION_F2};
@@ -164,16 +164,16 rtems_task Init( rtems_task_argument ign
164 164 init_k_coefficients_prc0();
165 165 init_k_coefficients_prc1();
166 166 init_k_coefficients_prc2();
167 pa_bia_status_info = 0x00;
168 cp_rpw_sc_rw_f_flags = 0x00;
169 cp_rpw_sc_rw1_f1 = 0.0;
170 cp_rpw_sc_rw1_f2 = 0.0;
171 cp_rpw_sc_rw2_f1 = 0.0;
172 cp_rpw_sc_rw2_f2 = 0.0;
173 cp_rpw_sc_rw3_f1 = 0.0;
174 cp_rpw_sc_rw3_f2 = 0.0;
175 cp_rpw_sc_rw4_f1 = 0.0;
176 cp_rpw_sc_rw4_f2 = 0.0;
167 pa_bia_status_info = INIT_CHAR;
168 cp_rpw_sc_rw_f_flags = INIT_CHAR;
169 cp_rpw_sc_rw1_f1 = INIT_FLOAT;
170 cp_rpw_sc_rw1_f2 = INIT_FLOAT;
171 cp_rpw_sc_rw2_f1 = INIT_FLOAT;
172 cp_rpw_sc_rw2_f2 = INIT_FLOAT;
173 cp_rpw_sc_rw3_f1 = INIT_FLOAT;
174 cp_rpw_sc_rw3_f2 = INIT_FLOAT;
175 cp_rpw_sc_rw4_f1 = INIT_FLOAT;
176 cp_rpw_sc_rw4_f2 = INIT_FLOAT;
177 177 // initialize filtering parameters
178 178 filterPar.spare_sy_lfr_pas_filter_enabled = DEFAULT_SY_LFR_PAS_FILTER_ENABLED;
179 179 filterPar.sy_lfr_pas_filter_modulus = DEFAULT_SY_LFR_PAS_FILTER_MODULUS;
@@ -319,17 +319,17 void init_local_mode_parameters( void )
319 319
320 320 for(i = 0; i<SEQ_CNT_NB_DEST_ID; i++)
321 321 {
322 sequenceCounters_TC_EXE[i] = 0x00;
323 sequenceCounters_TM_DUMP[i] = 0x00;
322 sequenceCounters_TC_EXE[i] = INIT_CHAR;
323 sequenceCounters_TM_DUMP[i] = INIT_CHAR;
324 324 }
325 sequenceCounters_SCIENCE_NORMAL_BURST = 0x00;
326 sequenceCounters_SCIENCE_SBM1_SBM2 = 0x00;
327 sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << 8;
325 sequenceCounters_SCIENCE_NORMAL_BURST = INIT_CHAR;
326 sequenceCounters_SCIENCE_SBM1_SBM2 = INIT_CHAR;
327 sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << TM_PACKET_SEQ_SHIFT;
328 328 }
329 329
330 330 void reset_local_time( void )
331 331 {
332 time_management_regs->ctrl = time_management_regs->ctrl | 0x02; // [0010] software reset, coarse time = 0x80000000
332 time_management_regs->ctrl = time_management_regs->ctrl | VAL_SOFTWARE_RESET; // [0010] software reset, coarse time = 0x80000000
333 333 }
334 334
335 335 void create_names( void ) // create all names for tasks and queues
@@ -403,7 +403,7 int create_all_tasks( void ) // create a
403 403 if (status == RTEMS_SUCCESSFUL) // SEND
404 404 {
405 405 status = rtems_task_create(
406 Task_name[TASKID_SEND], TASK_PRIORITY_SEND, RTEMS_MINIMUM_STACK_SIZE * 2,
406 Task_name[TASKID_SEND], TASK_PRIORITY_SEND, RTEMS_MINIMUM_STACK_SIZE * STACK_SIZE_MULT,
407 407 RTEMS_DEFAULT_MODES,
408 408 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_SEND]
409 409 );
@@ -446,7 +446,7 int create_all_tasks( void ) // create a
446 446 if (status == RTEMS_SUCCESSFUL) // PRC0
447 447 {
448 448 status = rtems_task_create(
449 Task_name[TASKID_PRC0], TASK_PRIORITY_PRC0, RTEMS_MINIMUM_STACK_SIZE * 2,
449 Task_name[TASKID_PRC0], TASK_PRIORITY_PRC0, RTEMS_MINIMUM_STACK_SIZE * STACK_SIZE_MULT,
450 450 RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT,
451 451 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC0]
452 452 );
@@ -462,7 +462,7 int create_all_tasks( void ) // create a
462 462 if (status == RTEMS_SUCCESSFUL) // PRC1
463 463 {
464 464 status = rtems_task_create(
465 Task_name[TASKID_PRC1], TASK_PRIORITY_PRC1, RTEMS_MINIMUM_STACK_SIZE * 2,
465 Task_name[TASKID_PRC1], TASK_PRIORITY_PRC1, RTEMS_MINIMUM_STACK_SIZE * STACK_SIZE_MULT,
466 466 RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT,
467 467 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC1]
468 468 );
@@ -478,7 +478,7 int create_all_tasks( void ) // create a
478 478 if (status == RTEMS_SUCCESSFUL) // PRC2
479 479 {
480 480 status = rtems_task_create(
481 Task_name[TASKID_PRC2], TASK_PRIORITY_PRC2, RTEMS_MINIMUM_STACK_SIZE * 2,
481 Task_name[TASKID_PRC2], TASK_PRIORITY_PRC2, RTEMS_MINIMUM_STACK_SIZE * STACK_SIZE_MULT,
482 482 RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT,
483 483 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC2]
484 484 );
@@ -913,10 +913,10 void init_ring(ring_node ring[], unsigne
913 913 // BUFFER ADDRESS
914 914 for(i=0; i<nbNodes; i++)
915 915 {
916 ring[i].coarseTime = 0xffffffff;
917 ring[i].fineTime = 0xffffffff;
918 ring[i].sid = 0x00;
919 ring[i].status = 0x00;
916 ring[i].coarseTime = INT32_ALL_F;
917 ring[i].fineTime = INT32_ALL_F;
918 ring[i].sid = INIT_CHAR;
919 ring[i].status = INIT_CHAR;
920 920 ring[i].buffer_address = (int) &buffer[ i * bufferSize ];
921 921 }
922 922
@@ -25,7 +25,7 void timer_configure(unsigned char timer
25 25 rtems_status_code status;
26 26 rtems_isr_entry old_isr_handler;
27 27
28 gptimer_regs->timer[timer].ctrl = 0x00; // reset the control register
28 gptimer_regs->timer[timer].ctrl = INIT_CHAR; // reset the control register
29 29
30 30 status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
31 31 if (status!=RTEMS_SUCCESSFUL)
@@ -45,11 +45,11 void timer_start(unsigned char timer)
45 45 *
46 46 */
47 47
48 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000010; // clear pending IRQ if any
49 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000004; // LD load value from the reload register
50 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000001; // EN enable the timer
51 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000002; // RS restart
52 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000008; // IE interrupt enable
48 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
49 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_LD;
50 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_EN;
51 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_RS;
52 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_IE;
53 53 }
54 54
55 55 void timer_stop(unsigned char timer)
@@ -61,9 +61,9 void timer_stop(unsigned char timer)
61 61 *
62 62 */
63 63
64 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & 0xfffffffe; // EN enable the timer
65 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & 0xffffffef; // IE interrupt enable
66 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000010; // clear pending IRQ if any
64 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_EN_MASK;
65 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_IE_MASK;
66 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
67 67 }
68 68
69 69 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider)
@@ -127,7 +127,7 void watchdog_reload(void)
127 127 *
128 128 */
129 129
130 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | 0x00000004; // LD load value from the reload register
130 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
131 131 }
132 132
133 133 void watchdog_start(void)
@@ -141,10 +141,10 void watchdog_start(void)
141 141
142 142 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG );
143 143
144 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | 0x00000010; // clear pending IRQ if any
145 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | 0x00000004; // LD load value from the reload register
146 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | 0x00000001; // EN enable the timer
147 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | 0x00000008; // IE interrupt enable
144 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_CLEAR_IRQ;
145 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
146 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_EN;
147 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_IE;
148 148
149 149 LEON_Unmask_interrupt( IRQ_GPTIMER_WATCHDOG );
150 150
@@ -210,14 +210,14 rtems_task load_task(rtems_task_argument
210 210 status = rtems_rate_monotonic_period( watchdog_period_id, WATCHDOG_PERIOD );
211 211 watchdog_reload();
212 212 i = i + 1;
213 if ( i == 10 )
213 if ( i == WATCHDOG_LOOP_PRINTF )
214 214 {
215 215 i = 0;
216 216 j = j + 1;
217 217 PRINTF1("%d\n", j)
218 218 }
219 219 #ifdef DEBUG_WATCHDOG
220 if (j == 3 )
220 if (j == WATCHDOG_LOOP_DEBUG )
221 221 {
222 222 status = rtems_task_delete(RTEMS_SELF);
223 223 }
@@ -261,15 +261,15 rtems_task hous_task(rtems_task_argument
261 261 DEBUG_PRINTF1("startup HK, HK_id status = %d\n", period_status.state)
262 262 while(period_status.state != RATE_MONOTONIC_EXPIRED ) // after SY_LFR_TIME_SYN_TIMEOUT ms, starts HK anyway
263 263 {
264 if ((time_management_regs->coarse_time & 0x80000000) == 0x00000000) // check time synchronization
264 if ((time_management_regs->coarse_time & VAL_LFR_SYNCHRONIZED) == INT32_ALL_0) // check time synchronization
265 265 {
266 266 break; // break if LFR is synchronized
267 267 }
268 268 else
269 269 {
270 270 status = rtems_rate_monotonic_get_status( HK_id, &period_status );
271 // sched_yield();
272 status = rtems_task_wake_after( 10 ); // wait SY_LFR_DPU_CONNECT_TIMEOUT 100 ms = 10 * 10 ms
271
272 status = rtems_task_wake_after( HK_SYNC_WAIT ); // wait HK_SYNCH_WAIT 100 ms = 10 * 10 ms
273 273 }
274 274 }
275 275 status = rtems_rate_monotonic_cancel(HK_id);
@@ -284,16 +284,16 rtems_task hous_task(rtems_task_argument
284 284 spare_status = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_6 );
285 285 }
286 286 else {
287 housekeeping_packet.packetSequenceControl[0] = (unsigned char) (sequenceCounterHK >> 8);
288 housekeeping_packet.packetSequenceControl[1] = (unsigned char) (sequenceCounterHK );
287 housekeeping_packet.packetSequenceControl[BYTE_0] = (unsigned char) (sequenceCounterHK >> SHIFT_1_BYTE);
288 housekeeping_packet.packetSequenceControl[BYTE_1] = (unsigned char) (sequenceCounterHK );
289 289 increment_seq_counter( &sequenceCounterHK );
290 290
291 housekeeping_packet.time[0] = (unsigned char) (time_management_regs->coarse_time>>24);
292 housekeeping_packet.time[1] = (unsigned char) (time_management_regs->coarse_time>>16);
293 housekeeping_packet.time[2] = (unsigned char) (time_management_regs->coarse_time>>8);
294 housekeeping_packet.time[3] = (unsigned char) (time_management_regs->coarse_time);
295 housekeeping_packet.time[4] = (unsigned char) (time_management_regs->fine_time>>8);
296 housekeeping_packet.time[5] = (unsigned char) (time_management_regs->fine_time);
291 housekeeping_packet.time[BYTE_0] = (unsigned char) (time_management_regs->coarse_time >> SHIFT_3_BYTES);
292 housekeeping_packet.time[BYTE_1] = (unsigned char) (time_management_regs->coarse_time >> SHIFT_2_BYTES);
293 housekeeping_packet.time[BYTE_2] = (unsigned char) (time_management_regs->coarse_time >> SHIFT_1_BYTE);
294 housekeeping_packet.time[BYTE_3] = (unsigned char) (time_management_regs->coarse_time);
295 housekeeping_packet.time[BYTE_4] = (unsigned char) (time_management_regs->fine_time >> SHIFT_1_BYTE);
296 housekeeping_packet.time[BYTE_5] = (unsigned char) (time_management_regs->fine_time);
297 297
298 298 spacewire_update_hk_lfr_link_state( &housekeeping_packet.lfr_status_word[0] );
299 299
@@ -436,22 +436,22 rtems_task dumb_task( rtems_task_argumen
436 436 unsigned int fine_time = 0;
437 437 rtems_event_set event_out;
438 438
439 char *DumbMessages[15] = {"in DUMB *** default", // RTEMS_EVENT_0
440 "in DUMB *** timecode_irq_handler", // RTEMS_EVENT_1
441 "in DUMB *** f3 buffer changed", // RTEMS_EVENT_2
442 "in DUMB *** in SMIQ *** Error sending event to AVF0", // RTEMS_EVENT_3
443 "in DUMB *** spectral_matrices_isr *** Error sending event to SMIQ", // RTEMS_EVENT_4
444 "in DUMB *** waveforms_simulator_isr", // RTEMS_EVENT_5
445 "VHDL SM *** two buffers f0 ready", // RTEMS_EVENT_6
446 "ready for dump", // RTEMS_EVENT_7
447 "VHDL ERR *** spectral matrix", // RTEMS_EVENT_8
448 "tick", // RTEMS_EVENT_9
449 "VHDL ERR *** waveform picker", // RTEMS_EVENT_10
450 "VHDL ERR *** unexpected ready matrix values", // RTEMS_EVENT_11
451 "WATCHDOG timer", // RTEMS_EVENT_12
452 "TIMECODE timer", // RTEMS_EVENT_13
453 "TIMECODE ISR" // RTEMS_EVENT_14
454 };
439 char *DumbMessages[DUMB_MESSAGE_NB] = {DUMB_MESSAGE_0, // RTEMS_EVENT_0
440 DUMB_MESSAGE_1, // RTEMS_EVENT_1
441 DUMB_MESSAGE_2, // RTEMS_EVENT_2
442 DUMB_MESSAGE_3, // RTEMS_EVENT_3
443 DUMB_MESSAGE_4, // RTEMS_EVENT_4
444 DUMB_MESSAGE_5, // RTEMS_EVENT_5
445 DUMB_MESSAGE_6, // RTEMS_EVENT_6
446 DUMB_MESSAGE_7, // RTEMS_EVENT_7
447 DUMB_MESSAGE_8, // RTEMS_EVENT_8
448 DUMB_MESSAGE_9, // RTEMS_EVENT_9
449 DUMB_MESSAGE_10, // RTEMS_EVENT_10
450 DUMB_MESSAGE_11, // RTEMS_EVENT_11
451 DUMB_MESSAGE_12, // RTEMS_EVENT_12
452 DUMB_MESSAGE_13, // RTEMS_EVENT_13
453 DUMB_MESSAGE_14 // RTEMS_EVENT_14
454 };
455 455
456 456 BOOT_PRINTF("in DUMB *** \n")
457 457
@@ -462,23 +462,23 rtems_task dumb_task( rtems_task_argumen
462 462 | RTEMS_EVENT_14,
463 463 RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT
464 464 intEventOut = (unsigned int) event_out;
465 for ( i=0; i<32; i++)
465 for ( i=0; i<NB_RTEMS_EVENTS; i++)
466 466 {
467 if ( ((intEventOut >> i) & 0x0001) != 0)
467 if ( ((intEventOut >> i) & 1) != 0)
468 468 {
469 469 coarse_time = time_management_regs->coarse_time;
470 470 fine_time = time_management_regs->fine_time;
471 if (i==12)
471 if (i==EVENT_12)
472 472 {
473 PRINTF1("%s\n", DumbMessages[12])
473 PRINTF1("%s\n", DUMB_MESSAGE_12)
474 474 }
475 if (i==13)
475 if (i==EVENT_13)
476 476 {
477 PRINTF1("%s\n", DumbMessages[13])
477 PRINTF1("%s\n", DUMB_MESSAGE_13)
478 478 }
479 if (i==14)
479 if (i==EVENT_14)
480 480 {
481 PRINTF1("%s\n", DumbMessages[1])
481 PRINTF1("%s\n", DUMB_MESSAGE_1)
482 482 }
483 483 }
484 484 }
@@ -504,18 +504,18 void init_housekeeping_parameters( void
504 504
505 505 for(i = 0; i< sizeOfHK; i++)
506 506 {
507 parameters[i] = 0x00;
507 parameters[i] = INIT_CHAR;
508 508 }
509 509
510 510 housekeeping_packet.targetLogicalAddress = CCSDS_DESTINATION_ID;
511 511 housekeeping_packet.protocolIdentifier = CCSDS_PROTOCOLE_ID;
512 512 housekeeping_packet.reserved = DEFAULT_RESERVED;
513 513 housekeeping_packet.userApplication = CCSDS_USER_APP;
514 housekeeping_packet.packetID[0] = (unsigned char) (APID_TM_HK >> 8);
514 housekeeping_packet.packetID[0] = (unsigned char) (APID_TM_HK >> SHIFT_1_BYTE);
515 515 housekeeping_packet.packetID[1] = (unsigned char) (APID_TM_HK);
516 516 housekeeping_packet.packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
517 517 housekeeping_packet.packetSequenceControl[1] = TM_PACKET_SEQ_CNT_DEFAULT;
518 housekeeping_packet.packetLength[0] = (unsigned char) (PACKET_LENGTH_HK >> 8);
518 housekeeping_packet.packetLength[0] = (unsigned char) (PACKET_LENGTH_HK >> SHIFT_1_BYTE);
519 519 housekeeping_packet.packetLength[1] = (unsigned char) (PACKET_LENGTH_HK );
520 520 housekeeping_packet.spare1_pusVersion_spare2 = DEFAULT_SPARE1_PUSVERSION_SPARE2;
521 521 housekeeping_packet.serviceType = TM_TYPE_HK;
@@ -529,13 +529,13 void init_housekeeping_parameters( void
529 529 // init software version
530 530 housekeeping_packet.lfr_sw_version[0] = SW_VERSION_N1;
531 531 housekeeping_packet.lfr_sw_version[1] = SW_VERSION_N2;
532 housekeeping_packet.lfr_sw_version[2] = SW_VERSION_N3;
533 housekeeping_packet.lfr_sw_version[3] = SW_VERSION_N4;
532 housekeeping_packet.lfr_sw_version[BYTE_2] = SW_VERSION_N3;
533 housekeeping_packet.lfr_sw_version[BYTE_3] = SW_VERSION_N4;
534 534 // init fpga version
535 535 parameters = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
536 housekeeping_packet.lfr_fpga_version[0] = parameters[1]; // n1
537 housekeeping_packet.lfr_fpga_version[1] = parameters[2]; // n2
538 housekeeping_packet.lfr_fpga_version[2] = parameters[3]; // n3
536 housekeeping_packet.lfr_fpga_version[BYTE_0] = parameters[BYTE_1]; // n1
537 housekeeping_packet.lfr_fpga_version[BYTE_1] = parameters[BYTE_2]; // n2
538 housekeeping_packet.lfr_fpga_version[BYTE_2] = parameters[BYTE_3]; // n3
539 539
540 540 housekeeping_packet.hk_lfr_q_sd_fifo_size = MSG_QUEUE_COUNT_SEND;
541 541 housekeeping_packet.hk_lfr_q_rv_fifo_size = MSG_QUEUE_COUNT_RECV;
@@ -555,8 +555,8 void increment_seq_counter( unsigned sho
555 555 unsigned short segmentation_grouping_flag;
556 556 unsigned short sequence_cnt;
557 557
558 segmentation_grouping_flag = TM_PACKET_SEQ_CTRL_STANDALONE << 8; // keep bits 7 downto 6
559 sequence_cnt = (*packetSequenceControl) & 0x3fff; // [0011 1111 1111 1111]
558 segmentation_grouping_flag = TM_PACKET_SEQ_CTRL_STANDALONE << SHIFT_1_BYTE; // keep bits 7 downto 6
559 sequence_cnt = (*packetSequenceControl) & SEQ_CNT_MASK; // [0011 1111 1111 1111]
560 560
561 561 if ( sequence_cnt < SEQ_CNT_MAX)
562 562 {
@@ -576,11 +576,11 void getTime( unsigned char *time)
576 576 *
577 577 */
578 578
579 time[0] = (unsigned char) (time_management_regs->coarse_time>>24);
580 time[1] = (unsigned char) (time_management_regs->coarse_time>>16);
581 time[2] = (unsigned char) (time_management_regs->coarse_time>>8);
579 time[0] = (unsigned char) (time_management_regs->coarse_time>>SHIFT_3_BYTES);
580 time[1] = (unsigned char) (time_management_regs->coarse_time>>SHIFT_2_BYTES);
581 time[2] = (unsigned char) (time_management_regs->coarse_time>>SHIFT_1_BYTE);
582 582 time[3] = (unsigned char) (time_management_regs->coarse_time);
583 time[4] = (unsigned char) (time_management_regs->fine_time>>8);
583 time[4] = (unsigned char) (time_management_regs->fine_time>>SHIFT_1_BYTE);
584 584 time[5] = (unsigned char) (time_management_regs->fine_time);
585 585 }
586 586
@@ -591,7 +591,7 unsigned long long int getTimeAsUnsigned
591 591 */
592 592 unsigned long long int time;
593 593
594 time = ( (unsigned long long int) (time_management_regs->coarse_time & 0x7fffffff) << 16 )
594 time = ( (unsigned long long int) (time_management_regs->coarse_time & COARSE_TIME_MASK) << SHIFT_2_BYTES )
595 595 + time_management_regs->fine_time;
596 596
597 597 return time;
@@ -608,43 +608,43 void send_dumb_hk( void )
608 608 dummy_hk_packet.protocolIdentifier = CCSDS_PROTOCOLE_ID;
609 609 dummy_hk_packet.reserved = DEFAULT_RESERVED;
610 610 dummy_hk_packet.userApplication = CCSDS_USER_APP;
611 dummy_hk_packet.packetID[0] = (unsigned char) (APID_TM_HK >> 8);
611 dummy_hk_packet.packetID[0] = (unsigned char) (APID_TM_HK >> SHIFT_1_BYTE);
612 612 dummy_hk_packet.packetID[1] = (unsigned char) (APID_TM_HK);
613 613 dummy_hk_packet.packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
614 614 dummy_hk_packet.packetSequenceControl[1] = TM_PACKET_SEQ_CNT_DEFAULT;
615 dummy_hk_packet.packetLength[0] = (unsigned char) (PACKET_LENGTH_HK >> 8);
615 dummy_hk_packet.packetLength[0] = (unsigned char) (PACKET_LENGTH_HK >> SHIFT_1_BYTE);
616 616 dummy_hk_packet.packetLength[1] = (unsigned char) (PACKET_LENGTH_HK );
617