HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/JEANDET/LFR_FSW Commit - r384:c56e87012e2b

Removed most unused macros...

jeandet -

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r384:c56e87012e2b

.hgsubstate +1 -1

@@ -1,2 +1,2
1	3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters	1	3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
2	321ffad81ce675a1ad47d6fec71f04137fd44501 header/lfr_common_headers	2	0adeb6c86feb96a126ce48641604949b87c70481 header/lfr_common_headers

header/fsw_misc.h 0 -14

             #include "fsw_spacewire.h"
             #include "lfr_cpu_usage_report.h"
-            #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0
             #define WATCHDOG_LOOP_PRINTF    10
             #define WATCHDOG_LOOP_DEBUG     3
-            #define DUMB_MESSAGE_NB 15
             #define NB_RTEMS_EVENTS 32
             #define EVENT_12        12
             #define EVENT_13        13
             #define EVENT_14        14
-            #define DUMB_MESSAGE_0  "in DUMB *** default"
             #define DUMB_MESSAGE_1  "in DUMB *** timecode_irq_handler"
-            #define DUMB_MESSAGE_2  "in DUMB *** f3 buffer changed"
-            #define DUMB_MESSAGE_3  "in DUMB *** in SMIQ *** Error sending event to AVF0"
-            #define DUMB_MESSAGE_4  "in DUMB *** spectral_matrices_isr *** Error sending event to SMIQ"
-            #define DUMB_MESSAGE_5  "in DUMB *** waveforms_simulator_isr"
-            #define DUMB_MESSAGE_6  "VHDL SM *** two buffers f0 ready"
-            #define DUMB_MESSAGE_7  "ready for dump"
-            #define DUMB_MESSAGE_8  "VHDL ERR *** spectral matrix"
-            #define DUMB_MESSAGE_9  "tick"
-            #define DUMB_MESSAGE_10 "VHDL ERR *** waveform picker"
-            #define DUMB_MESSAGE_11 "VHDL ERR *** unexpected ready matrix values"
             #define DUMB_MESSAGE_12 "WATCHDOG timer"
             #define DUMB_MESSAGE_13 "TIMECODE timer"
-            #define DUMB_MESSAGE_14 "TIMECODE ISR"
             enum lfr_reset_cause_t{
                 UNKNOWN_CAUSE,

header/lfr_cpu_usage_report.h 0 -1

             #define CONST_100       100
             #define CONST_255       255
             #define CONST_1000      1000
-            #define CONST_100000    100000
             #endif // LFR_CPU_USAGE_REPORT_H

header/processing/fsw_processing.h 0 -9

@@ -15,15 +15,6
15	#define MAX_SRC_DATA 780 // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]	15	#define MAX_SRC_DATA 780 // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
16	#define MAX_SRC_DATA_WITH_SPARE 143 // 13 bins * 11 Bytes	16	#define MAX_SRC_DATA_WITH_SPARE 143 // 13 bins * 11 Bytes
17		17
18	#define NODE_0 0
19	#define NODE_1 1
20	#define NODE_2 2
21	#define NODE_3 3
22	#define NODE_4 4
23	#define NODE_5 5
24	#define NODE_6 6
25	#define NODE_7 7
26
27	typedef struct ring_node_asm	18	typedef struct ring_node_asm
28	{	19	{
29	struct ring_node_asm *next;	20	struct ring_node_asm *next;

header/tc_load_dump_parameters.h 0 -10

@@ -19,16 +19,6
19	#define DELTAF_F0 96.	19	#define DELTAF_F0 96.
20	#define DELTAF_F1 16.	20	#define DELTAF_F1 16.
21	#define DELTAF_F2 1.	21	#define DELTAF_F2 1.
22	#define DELTAF_DIV 2.
23
24	#define BIT_RW1_F1 0x80
25	#define BIT_RW1_F2 0x40
26	#define BIT_RW2_F1 0x20
27	#define BIT_RW2_F2 0x10
28	#define BIT_RW3_F1 0x08
29	#define BIT_RW3_F2 0x04
30	#define BIT_RW4_F1 0x02
31	#define BIT_RW4_F2 0x01
32		22
33	#define WHEEL_1 1	23	#define WHEEL_1 1
34	#define WHEEL_2 2	24	#define WHEEL_2 2

header/wf_handler.h 0 -1

             #define FREQ_F0     24576.
             #define FREQ_F1     4096.
             #define FREQ_F2     256.
-            #define FREQ_F3     16.
             #define DELTAT_F0   2731    // (2048. / 24576. / 2.) * 65536. = 2730.667;
             #define DELTAT_F1   16384   // (2048. / 4096.  / 2.) * 65536. = 16384;

testbenches/fsw_matrices_handling/functions.h 0 -1

             #define NB_BINS_COMPRESSED_SM_F0    11
             #define ASM_F0_INDICE_START         17      // 88 bins
-            #define ASM_F0_INDICE_STOP          104     // 2 packets of 44 bins
             #define NB_BINS_TO_AVERAGE_ASM_F0   8
             void ASM_reorganize_and_divide( float *averaged_spec_mat, float *averaged_spec_mat_reorganized, float divider )

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