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1 | 1 | 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters |
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2 | 321ffad81ce675a1ad47d6fec71f04137fd44501 header/lfr_common_headers | |
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2 | 0adeb6c86feb96a126ce48641604949b87c70481 header/lfr_common_headers | |
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10 | 10 | #include "fsw_spacewire.h" |
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11 | 11 | #include "lfr_cpu_usage_report.h" |
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12 | 12 | |
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13 | #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0 | |
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14 | 13 | #define WATCHDOG_LOOP_PRINTF 10 |
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15 | 14 | #define WATCHDOG_LOOP_DEBUG 3 |
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16 | 15 | |
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17 | #define DUMB_MESSAGE_NB 15 | |
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18 | 16 | #define NB_RTEMS_EVENTS 32 |
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19 | 17 | #define EVENT_12 12 |
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20 | 18 | #define EVENT_13 13 |
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21 | 19 | #define EVENT_14 14 |
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22 | #define DUMB_MESSAGE_0 "in DUMB *** default" | |
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23 | 20 | #define DUMB_MESSAGE_1 "in DUMB *** timecode_irq_handler" |
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24 | #define DUMB_MESSAGE_2 "in DUMB *** f3 buffer changed" | |
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25 | #define DUMB_MESSAGE_3 "in DUMB *** in SMIQ *** Error sending event to AVF0" | |
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26 | #define DUMB_MESSAGE_4 "in DUMB *** spectral_matrices_isr *** Error sending event to SMIQ" | |
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27 | #define DUMB_MESSAGE_5 "in DUMB *** waveforms_simulator_isr" | |
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28 | #define DUMB_MESSAGE_6 "VHDL SM *** two buffers f0 ready" | |
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29 | #define DUMB_MESSAGE_7 "ready for dump" | |
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30 | #define DUMB_MESSAGE_8 "VHDL ERR *** spectral matrix" | |
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31 | #define DUMB_MESSAGE_9 "tick" | |
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32 | #define DUMB_MESSAGE_10 "VHDL ERR *** waveform picker" | |
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33 | #define DUMB_MESSAGE_11 "VHDL ERR *** unexpected ready matrix values" | |
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34 | 21 | #define DUMB_MESSAGE_12 "WATCHDOG timer" |
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35 | 22 | #define DUMB_MESSAGE_13 "TIMECODE timer" |
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36 | #define DUMB_MESSAGE_14 "TIMECODE ISR" | |
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37 | 23 | |
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38 | 24 | enum lfr_reset_cause_t{ |
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39 | 25 | UNKNOWN_CAUSE, |
| @@ -33,6 +33,5 unsigned char lfr_rtems_cpu_usage_report | |||
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33 | 33 | #define CONST_100 100 |
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34 | 34 | #define CONST_255 255 |
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35 | 35 | #define CONST_1000 1000 |
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36 | #define CONST_100000 100000 | |
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37 | 36 | |
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38 | 37 | #endif // LFR_CPU_USAGE_REPORT_H |
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15 | 15 | #define MAX_SRC_DATA 780 // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1] |
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16 | 16 | #define MAX_SRC_DATA_WITH_SPARE 143 // 13 bins * 11 Bytes |
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17 | 17 | |
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18 | #define NODE_0 0 | |
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19 | #define NODE_1 1 | |
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20 | #define NODE_2 2 | |
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21 | #define NODE_3 3 | |
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22 | #define NODE_4 4 | |
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23 | #define NODE_5 5 | |
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24 | #define NODE_6 6 | |
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25 | #define NODE_7 7 | |
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26 | ||
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27 | 18 | typedef struct ring_node_asm |
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28 | 19 | { |
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29 | 20 | struct ring_node_asm *next; |
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19 | 19 | #define DELTAF_F0 96. |
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20 | 20 | #define DELTAF_F1 16. |
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21 | 21 | #define DELTAF_F2 1. |
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22 | #define DELTAF_DIV 2. | |
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23 | ||
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24 | #define BIT_RW1_F1 0x80 | |
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25 | #define BIT_RW1_F2 0x40 | |
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26 | #define BIT_RW2_F1 0x20 | |
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27 | #define BIT_RW2_F2 0x10 | |
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28 | #define BIT_RW3_F1 0x08 | |
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29 | #define BIT_RW3_F2 0x04 | |
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30 | #define BIT_RW4_F1 0x02 | |
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31 | #define BIT_RW4_F2 0x01 | |
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32 | 22 | |
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33 | 23 | #define WHEEL_1 1 |
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34 | 24 | #define WHEEL_2 2 |
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24 | 24 | #define FREQ_F0 24576. |
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25 | 25 | #define FREQ_F1 4096. |
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26 | 26 | #define FREQ_F2 256. |
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27 | #define FREQ_F3 16. | |
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28 | 27 | |
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29 | 28 | #define DELTAT_F0 2731 // (2048. / 24576. / 2.) * 65536. = 2730.667; |
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30 | 29 | #define DELTAT_F1 16384 // (2048. / 4096. / 2.) * 65536. = 16384; |
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3 | 3 | |
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4 | 4 | #define NB_BINS_COMPRESSED_SM_F0 11 |
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5 | 5 | #define ASM_F0_INDICE_START 17 // 88 bins |
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6 | #define ASM_F0_INDICE_STOP 104 // 2 packets of 44 bins | |
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7 | 6 | #define NB_BINS_TO_AVERAGE_ASM_F0 8 |
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8 | 7 | |
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9 | 8 | void ASM_reorganize_and_divide( float *averaged_spec_mat, float *averaged_spec_mat_reorganized, float divider ) |
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