@@ -1,7 +1,15 | |||||
1 | TEMPLATE = app |
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1 | TEMPLATE = app | |
2 | # CONFIG += console v8 sim |
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2 | # CONFIG += console v8 sim | |
3 | # CONFIG options = verbose *** boot_messages *** debug_messages *** cpu_usage_report *** stack_report *** vhdl_dev *** debug_tch |
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3 | # CONFIG options = | |
4 | # lpp_dpu_destid |
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4 | # verbose | |
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5 | # boot_messages | |||
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6 | # debug_messages | |||
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7 | # cpu_usage_report | |||
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8 | # stack_report | |||
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9 | # vhdl_dev | |||
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10 | # debug_tch | |||
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11 | # lpp_dpu_destid REMOVE BEFORE DELIVERY TO LESIA | |||
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12 | # debug_watchdog | |||
5 | CONFIG += console verbose lpp_dpu_destid |
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13 | CONFIG += console verbose lpp_dpu_destid | |
6 | CONFIG -= qt |
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14 | CONFIG -= qt | |
7 |
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15 | |||
@@ -12,7 +20,7 SWVERSION=-1-0 | |||||
12 | DEFINES += SW_VERSION_N1=3 # major |
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20 | DEFINES += SW_VERSION_N1=3 # major | |
13 | DEFINES += SW_VERSION_N2=0 # minor |
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21 | DEFINES += SW_VERSION_N2=0 # minor | |
14 | DEFINES += SW_VERSION_N3=0 # patch |
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22 | DEFINES += SW_VERSION_N3=0 # patch | |
15 |
DEFINES += SW_VERSION_N4=1 |
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23 | DEFINES += SW_VERSION_N4=14 # internal | |
16 |
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24 | |||
17 | # <GCOV> |
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25 | # <GCOV> | |
18 | #QMAKE_CFLAGS_RELEASE += -fprofile-arcs -ftest-coverage |
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26 | #QMAKE_CFLAGS_RELEASE += -fprofile-arcs -ftest-coverage |
@@ -5,65 +5,188 | |||||
5 | #define LEON3 |
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5 | #define LEON3 | |
6 | #endif |
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6 | #endif | |
7 |
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7 | |||
8 | static unsigned int getCacheControlRegister(){ |
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8 | #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000 | |
9 | #ifdef LEON3 |
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9 | #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only) | |
10 | unsigned int cacheControlRegister = 0; |
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10 | ||
11 | __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : ); |
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11 | #define DEVICEID_LEON3 0x003 | |
12 | return cacheControlRegister; |
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12 | #define DEVICEID_LEON3FT 0x053 | |
13 | #endif |
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13 | #define VENDORID_GAISLER 0x01 | |
14 | } |
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15 |
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14 | |||
16 | static void setCacheControlRegister(unsigned int cacheControlRegister) |
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15 | // CCR | |
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16 | #define POS_ITE 12 | |||
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17 | #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000 | |||
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18 | #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111 | |||
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19 | #define POS_IDE 10 | |||
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20 | #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000 | |||
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21 | #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111 | |||
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22 | // | |||
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23 | #define POS_DTE 8 | |||
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24 | #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000 | |||
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25 | #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111 | |||
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26 | #define POS_DDE 6 | |||
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27 | #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000 | |||
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28 | #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111 | |||
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29 | ||||
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30 | // ASR16 | |||
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31 | #define POS_FPRF 27 | |||
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32 | #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000 | |||
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33 | #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111 | |||
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34 | #define POS_IURF 11 | |||
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35 | #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000 | |||
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36 | #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111 | |||
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37 | ||||
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38 | volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS; | |||
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39 | ||||
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40 | static inline void flushCache() | |||
17 | { |
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41 | { | |
18 | #ifdef LEON3 |
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42 | /** | |
19 | __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister)); |
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43 | * Flush the data cache and the instruction cache. | |
20 | #endif |
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44 | * | |
21 | } |
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45 | * @param void | |
22 |
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46 | * | ||
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47 | * @return void | |||
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48 | */ | |||
23 |
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49 | |||
24 | /** |
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|||
25 | * Flush the data cache and the instruction cache. |
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|||
26 | * |
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|||
27 | * @return |
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|||
28 | */ |
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|||
29 | static inline void flushCache() { |
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30 | asm("flush"); |
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50 | asm("flush"); | |
31 | } |
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51 | } | |
32 |
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52 | |||
33 | static void resetCacheControlRegister() { |
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53 | //*************************** | |
34 | #ifdef LEON3 |
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54 | // CCR Cache control register | |
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55 | ||||
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56 | static unsigned int CCR_getValue() | |||
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57 | { | |||
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58 | unsigned int cacheControlRegister = 0; | |||
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59 | __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : ); | |||
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60 | return cacheControlRegister; | |||
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61 | } | |||
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62 | ||||
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63 | static void CCR_setValue(unsigned int cacheControlRegister) | |||
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64 | { | |||
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65 | __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister)); | |||
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66 | } | |||
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67 | ||||
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68 | static void CCR_resetCacheControlRegister() | |||
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69 | { | |||
35 | unsigned int cacheControlRegister; |
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70 | unsigned int cacheControlRegister; | |
36 | cacheControlRegister = 0x00; |
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71 | cacheControlRegister = 0x00; | |
37 |
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72 | CCR_setValue(cacheControlRegister); | |
38 | #endif |
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73 | } | |
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74 | ||||
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75 | static void CCR_enableInstructionCache() | |||
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76 | { | |||
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77 | // [1:0] Instruction Cache state (ICS) | |||
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78 | // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled. | |||
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79 | unsigned int cacheControlRegister; | |||
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80 | cacheControlRegister = CCR_getValue(); | |||
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81 | cacheControlRegister = (cacheControlRegister | 0x3); | |||
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82 | CCR_setValue(cacheControlRegister); | |||
39 | } |
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83 | } | |
40 |
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84 | |||
41 |
static void enable |
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85 | static void CCR_enableDataCache() | |
42 | #ifdef LEON3 |
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86 | { | |
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87 | // [3:2] Data Cache state (DCS) | |||
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88 | // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled. | |||
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89 | unsigned int cacheControlRegister; | |||
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90 | cacheControlRegister = CCR_getValue(); | |||
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91 | cacheControlRegister = (cacheControlRegister | 0xc); | |||
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92 | CCR_setValue(cacheControlRegister); | |||
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93 | } | |||
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94 | ||||
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95 | static void CCR_faultTolerantScheme() | |||
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96 | { | |||
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97 | // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented | |||
43 | unsigned int cacheControlRegister; |
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98 | unsigned int cacheControlRegister; | |
44 | cacheControlRegister = getCacheControlRegister(); |
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99 | unsigned int *plugAndPlayRegister; | |
45 | cacheControlRegister = (cacheControlRegister | 0x3); |
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100 | unsigned int vendorId; | |
46 | setCacheControlRegister(cacheControlRegister); |
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101 | unsigned int deviceId; | |
47 | #endif |
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102 | ||
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103 | plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY; | |||
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104 | vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24; | |||
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105 | deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12; | |||
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106 | ||||
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107 | if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) ) | |||
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108 | { | |||
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109 | PRINTF("in faultTolerantScheme *** Leon3FT detected, configure the CCR FT bits"); | |||
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110 | cacheControlRegister = CCR_getValue(); | |||
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111 | cacheControlRegister = (cacheControlRegister | 0xc); | |||
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112 | CCR_setValue(cacheControlRegister); | |||
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113 | } | |||
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114 | else | |||
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115 | { | |||
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116 | PRINTF("in faultTolerantScheme *** not a Leon3FT, no need to configure the CCR FT bits\n"); | |||
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117 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); | |||
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118 | } | |||
48 | } |
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119 | } | |
49 |
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120 | |||
50 |
static void enable |
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121 | static void CCR_enableInstructionBurstFetch() | |
51 | #ifdef LEON3 |
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122 | { | |
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123 | // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch. | |||
52 | unsigned int cacheControlRegister; |
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124 | unsigned int cacheControlRegister; | |
53 |
cacheControlRegister = |
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125 | cacheControlRegister = CCR_getValue(); | |
54 | cacheControlRegister = (cacheControlRegister | 0xc); |
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126 | // set the bit IB to 1 | |
55 |
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127 | cacheControlRegister = (cacheControlRegister | 0x10000); | |
56 | #endif |
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128 | CCR_setValue(cacheControlRegister); | |
57 | } |
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129 | } | |
58 |
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130 | |||
59 | static void enableInstructionBurstFetch() { |
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131 | static void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter ) | |
60 | #ifdef LEON3 |
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132 | { | |
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133 | // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache. | |||
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134 | // Only available if fault-tolerance is enabled (FT field in this register is non-zero). | |||
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135 | // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache. | |||
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136 | // Only available if fault-tolerance is enabled (FT field in this register is non-zero). | |||
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137 | ||||
61 | unsigned int cacheControlRegister; |
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138 | unsigned int cacheControlRegister; | |
62 | cacheControlRegister = getCacheControlRegister(); |
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139 | unsigned int iTE; | |
63 | // set the bit IB to 1 |
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140 | unsigned int iDE; | |
64 | cacheControlRegister = (cacheControlRegister | 0x10000); |
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141 | unsigned int dTE; | |
65 | setCacheControlRegister(cacheControlRegister); |
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142 | unsigned int dDE; | |
66 | #endif |
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143 | ||
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144 | cacheControlRegister = CCR_getValue(); | |||
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145 | iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE; | |||
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146 | iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE; | |||
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147 | dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE; | |||
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148 | dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE; | |||
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149 | ||||
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150 | *instructionErrorCounter = iTE + iDE; | |||
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151 | *dataErrorCounter = dTE + dDE; | |||
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152 | ||||
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153 | // reset counters | |||
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154 | cacheControlRegister = cacheControlRegister | |||
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155 | & COUNTER_FIELD_ITE | |||
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156 | & COUNTER_FIELD_IDE | |||
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157 | & COUNTER_FIELD_DTE | |||
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158 | & COUNTER_FIELD_DDE; | |||
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159 | ||||
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160 | CCR_setValue(cacheControlRegister); | |||
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161 | } | |||
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162 | ||||
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163 | //******************************************* | |||
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164 | // ASR16 Register protection control register | |||
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165 | ||||
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166 | static unsigned int ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter) | |||
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167 | { | |||
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168 | /** This function is used to retrieve the integer unit register file error counter and the floating point unit | |||
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169 | * register file error counter | |||
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170 | * | |||
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171 | * @return void | |||
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172 | * | |||
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173 | * [29:27] FP RF error counter - Number of detected parity errors in the FP register file. | |||
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174 | * [13:11] IU RF error counter - Number of detected parity errors in the IU register file. | |||
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175 | * | |||
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176 | */ | |||
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177 | ||||
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178 | unsigned int asr16; | |||
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179 | ||||
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180 | asr16 = *asr16Ptr; | |||
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181 | *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF; | |||
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182 | *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF; | |||
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183 | ||||
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184 | // reset the counter to 0 | |||
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185 | asr16 = asr16Ptr | |||
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186 | & COUNTER_MASK_FPRF | |||
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187 | & COUNTER_FIELD_IURF; | |||
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188 | ||||
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189 | *asr16Ptr = asr16; | |||
67 | } |
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190 | } | |
68 |
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191 | |||
69 | #endif /* GSCMEMORY_HPP_ */ |
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192 | #endif /* GSCMEMORY_HPP_ */ |
@@ -64,19 +64,38 | |||||
64 |
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64 | |||
65 | void initCache() |
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65 | void initCache() | |
66 | { |
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66 | { | |
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67 | // ASI 2 contains a few control registers that have not been assigned as ancillary state registers. | |||
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68 | // These should only be read and written using 32-bit LDA/STA instructions. | |||
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69 | // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2. | |||
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70 | // The table below shows the register addresses: | |||
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71 | // 0x00 Cache control register | |||
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72 | // 0x04 Reserved | |||
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73 | // 0x08 Instruction cache configuration register | |||
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74 | // 0x0C Data cache configuration register | |||
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75 | ||||
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76 | // Cache Control Register Leon3 / Leon3FT | |||
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77 | // 31..30 29 28 27..24 23 22 21 20..19 18 17 16 | |||
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78 | // RFT PS TB DS FD FI FT ST IB | |||
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79 | // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0 | |||
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80 | // IP DP ITE IDE DTE DDE DF IF DCS ICS | |||
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81 | ||||
67 | unsigned int cacheControlRegister; |
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82 | unsigned int cacheControlRegister; | |
68 |
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83 | |||
69 |
cacheControlRegister = |
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84 | cacheControlRegister = CCR_getValue(); | |
70 | PRINTF1("(0) cacheControlRegister = %x\n", cacheControlRegister) |
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85 | PRINTF1("(0) cacheControlRegister = %x\n", cacheControlRegister); | |
71 |
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86 | |||
72 | resetCacheControlRegister(); |
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87 | CCR_resetCacheControlRegister(); | |
73 |
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88 | |||
74 | enableInstructionCache(); |
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89 | CCR_enableInstructionCache(); // ICS bits | |
75 | enableDataCache(); |
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90 | CCR_enableDataCache(); // DCS bits | |
76 | enableInstructionBurstFetch(); |
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91 | CCR_enableInstructionBurstFetch(); // IB bit | |
77 |
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92 | |||
78 |
cacheControlRegister = |
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93 | cacheControlRegister = CCR_getValue(); | |
79 | PRINTF1("(1) cacheControlRegister = %x\n", cacheControlRegister) |
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94 | PRINTF1("(1) cacheControlRegister = %x\n", cacheControlRegister); | |
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95 | ||||
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96 | CCR_faultTolerantScheme(); | |||
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97 | ||||
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98 | // FT activation | |||
80 | } |
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99 | } | |
81 |
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100 | |||
82 | rtems_task Init( rtems_task_argument ignored ) |
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101 | rtems_task Init( rtems_task_argument ignored ) |
@@ -117,6 +117,9 void watchdog_reload(void) | |||||
117 | { |
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117 | { | |
118 | /** This function reloads the watchdog timer counter with the timer reload value. |
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118 | /** This function reloads the watchdog timer counter with the timer reload value. | |
119 | * |
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119 | * | |
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120 | * @param void | |||
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121 | * | |||
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122 | * @return void | |||
120 | * |
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123 | * | |
121 | */ |
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124 | */ | |
122 |
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125 |
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