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HG_REPOSITORIES » LPP » INSTRUMENTATION » SocExplorerPlugins
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Fixed mistake on dsu3plugin.
jeandet -
r45:33514237ed3a default
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@@ -35,7 +35,7 struct acceptedMemctrlr_str
35
35
36 const struct acceptedMemctrlr_str acceptedMemctrlr[]=
36 const struct acceptedMemctrlr_str acceptedMemctrlr[]=
37 {
37 {
38 {0x01,0x04,"MCTRL"},
38 {0x0f,0x04,"MCTRL"},
39 {0x01,0x51,"FTSRCTRL"},
39 {0x01,0x51,"FTSRCTRL"},
40 {0x20,0x01,"SRCTRLE_0WS" },
40 {0x20,0x01,"SRCTRLE_0WS" },
41 {0x20,0x02,"SRCTRLE_1WS" }
41 {0x20,0x02,"SRCTRLE_1WS" }
@@ -97,11 +97,15 bool dsu3plugin::configureTarget()
97 for(int i=0; i<acceptedMemctrlrCnt;i++)
97 for(int i=0; i<acceptedMemctrlrCnt;i++)
98 {
98 {
99 MCTRLBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,acceptedMemctrlr[i].vid , acceptedMemctrlr[i].pid,0);
99 MCTRLBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,acceptedMemctrlr[i].vid , acceptedMemctrlr[i].pid,0);
100 if(MCTRLBASEADDRESS != (unsigned int)-1) break;
100 if(MCTRLBASEADDRESS != (unsigned int)-1)
101 {
102 SocExplorerEngine::message(this,QString("Found %1 @%2").arg(acceptedMemctrlr[i].name).arg(MCTRLBASEADDRESS,8,16),1);
103 break;
104 }
101 }
105 }
102 if(MCTRLBASEADDRESS == (unsigned int)-1)
106 if(MCTRLBASEADDRESS == (unsigned int)-1)
103 {
107 {
104 //SocExplorerEngine::message(this,"Can't find FTMemCtrlr",1);
108 SocExplorerEngine::message(this,"Can't any compatible memory controller",1);
105 return false;
109 return false;
106 }
110 }
107
111
@@ -174,16 +178,17 bool dsu3plugin::setCacheEnable(bool ena
174 if(DSUBASEADDRESS == (unsigned int)-1)
178 if(DSUBASEADDRESS == (unsigned int)-1)
175 DSUBASEADDRESS = 0x90000000;
179 DSUBASEADDRESS = 0x90000000;
176 WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
180 WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
181 unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
177 if(enabled)
182 if(enabled)
178 {
183 {
179 WriteRegs(uIntlist()<<0x0001000F,DSUBASEADDRESS+0x700000);
184 WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
180 //flushes cache.
185 //flushes cache.
181 WriteRegs(uIntlist()<<0x0061000F,DSUBASEADDRESS+0x700000);
186 WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
182 }
187 }
183 else
188 else
184 {
189 {
185 WriteRegs(uIntlist()<<0x00000000,DSUBASEADDRESS+0x700000);
190 WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
186 WriteRegs(uIntlist()<<0x00600000,DSUBASEADDRESS+0x700000);
191 WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
187 }
192 }
188 return true;
193 return true;
189 }
194 }
@@ -240,6 +245,13 void dsu3plugin::WriteRegs(uIntlist Valu
240 free(buff);
245 free(buff);
241 }
246 }
242
247
248 unsigned int dsu3plugin::ReadReg(unsigned int address)
249 {
250 unsigned int buff;
251 parent->Read(&buff,1,address);
252 return buff;
253 }
254
243 void dsu3plugin::writeSection(int index)
255 void dsu3plugin::writeSection(int index)
244 {
256 {
245 char* buffch=NULL;
257 char* buffch=NULL;
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@@ -57,6 +57,7 signals:
57 void updateInfo(elfparser* parser);
57 void updateInfo(elfparser* parser);
58 private:
58 private:
59 void WriteRegs(uIntlist Values, unsigned int address);
59 void WriteRegs(uIntlist Values, unsigned int address);
60 unsigned int ReadReg(unsigned int address);
60 void writeSection(int index);
61 void writeSection(int index);
61 void writeSection(const QString& name);
62 void writeSection(const QString& name);
62 dsu3pluginui* UI;
63 dsu3pluginui* UI;
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