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Updated LPP IPs registers definition list(LPP.xml)....
Jeandet Alexis -
r101:e14ed2d591b3 0.6
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1 <?xml version='1.0' encoding='utf-8'?>
1 <?xml version='1.0' encoding='utf-8'?>
2 <soc name="Leon">
2 <soc name="Leon">
3 <peripheral vid="25" name="LPP_APB_DAC" pid="7">
3 <peripheral vid="25" name="LPP_APB_DAC" pid="7">
4 <register name="DAC Control" addOffset="0">
4 <register name="DAC Control" addOffset="0">
5 <bitField size="2" offset="0" name="Dac config" mode="3" desc="Set the two configuration bits of the DAC ‘00’ mean normal operation, ‘01’ mean 1kOhms connected to GND, ‘10’ mean 100kOhms connected to GND, ‘11’ mean high impedance"/>
5 <bitField size="2" offset="0" name="Dac config" mode="3" desc="Set the two configuration bits of the DAC ‘00’ mean normal operation, ‘01’ mean 1kOhms connected to GND, ‘10’ mean 100kOhms connected to GND, ‘11’ mean high impedance"/>
6 <bitField size="1" offset="4" name="Reload" mode="3" desc="Reload freq divider to the value N, can be used also to stop dac"/>
6 <bitField size="1" offset="4" name="Reload" mode="3" desc="Reload freq divider to the value N, can be used also to stop dac"/>
7 <bitField name="Interleavde" offset="5" size="1" mode="3" desc="Set interleaved mode"/>
7 <bitField name="Interleavde" offset="5" size="1" mode="3" desc="Set interleaved mode"/>
8 </register>
8 </register>
9 <register name="Prescaller" addOffset="4">
9 <register name="Prescaller" addOffset="4">
10 <bitField size="32" offset="0" name="Pre" mode="3" desc="Set the prescaller division"/>
10 <bitField size="32" offset="0" name="Pre" mode="3" desc="Set the prescaller division"/>
11 </register>
11 </register>
12 <register name="Div" addOffset="8">
12 <register name="Div" addOffset="8">
13 <bitField size="32" offset="0" name="N" mode="3" desc="Set the division factor"/>
13 <bitField size="32" offset="0" name="N" mode="3" desc="Set the division factor"/>
14 </register>
14 </register>
15 <register name="Address" addOffset="12">
15 <register name="Address" addOffset="12">
16 <bitField size="32" offset="0" name="Address" mode="3" desc="Set the DAC RAM buffer address pointer"/>
16 <bitField size="32" offset="0" name="Address" mode="3" desc="Set the DAC RAM buffer address pointer"/>
17 </register>
17 </register>
18 <register name="DATA" addOffset="16">
18 <register name="DATA" addOffset="16">
19 <bitField size="32" offset="0" name="DATA" mode="3" desc="DATA to be written in the DAC RAM buffer"/>
19 <bitField size="32" offset="0" name="DATA" mode="3" desc="DATA to be written in the DAC RAM buffer"/>
20 </register>
20 </register>
21 </peripheral>
21 </peripheral>
22 <peripheral vid="25" name="LPP_LFR_MANAGEMENT" pid="34">
22 <peripheral vid="25" name="LPP_LFR_MANAGEMENT" pid="34">
23 <register name="CONTROL" addOffset="0">
23 <register name="CONTROL" addOffset="0">
24 <bitField size="1" offset="0" name="ctrl" mode="3" desc="NC"/>
24 <bitField size="1" offset="0" name="SWTick" mode="3" desc="Time Management Software tick."/>
25 <bitField size="1" offset="1" name="Soft Reset" mode="3" desc="NC "/>
25 <bitField size="1" offset="1" name="Soft Reset" mode="3" desc="Time Management Software Reset."/>
26 <bitField name="LFR Soft Reset" offset="5" size="1" mode="3" desc="NC"/>
26 <bitField size="1" offset="2" name="LFR Soft Reset" mode="3" desc="LFR SubSystem soft Reset."/>
27 </register>
28 <register name="TIME_LOAD" addOffset="4">
29 <bitField size="31" offset="0" name="Coarse Time Next" mode="3" desc="If modified, will set the next value of the coarse time."/>
27 </register>
30 </register>
28 <register name="COARSE TIME LOAD" addOffset="4">
31 <register name="TIME_COARS" addOffset="8">
29 <bitField size="31" offset="0" name="Coarse Time Load" mode="3" desc="NC"/>
32 <bitField size="31" offset="0" name="Coarse Time" mode="1" desc="Current coars time."/>
33 <bitField size="1" offset="31" name="UnSychronized" mode="1" desc="Tels if LFR is synchronyzed."/>
30 </register>
34 </register>
31 <register name="COARSE TIME" addOffset="8">
35 <register name="TIME_FINE" addOffset="12">
32 <bitField size="31" offset="0" name="Coarse Time" mode="1" desc="NC"/>
36 <bitField size="31" offset="0" name="Fine Time" mode="1" desc="Current fine time."/>
33 </register>
37 </register>
34 <register name="TEMP0" addOffset="12">
38 <register name="HK_TEMP_0" addOffset="16">
35 <bitField size="16" offset="0" name="HK Temperature 0" mode="1" desc="NC"/>
39 <bitField size="16" offset="0" name="HK Temperature 0" mode="1" desc="NC"/>
36 </register>
40 </register>
37 <register name="TEMP1" addOffset="16">
41 <register name="HK_TEMP_1" addOffset="20">
38 <bitField size="16" offset="0" name="HK Temperature 1" mode="1" desc="NC"/>
42 <bitField size="16" offset="0" name="HK Temperature 1" mode="1" desc="NC"/>
39 </register>
43 </register>
40 <register name="TEMP2" addOffset="20">
44 <register name="HK_TEMP_2" addOffset="24">
41 <bitField size="16" offset="0" name="HK Temperature 2" mode="1" desc="NC"/>
45 <bitField size="16" offset="0" name="HK Temperature 2" mode="1" desc="NC"/>
42 </register>
46 </register>
43 <register name="DAC Control" addOffset="24">
47 <register name="DAC_CONTROL" addOffset="28">
44 <bitField size="2" offset="0" name="Dac config" mode="3" desc="Set the two configuration bits of the DAC ‘00’ mean normal operation, ‘01’ mean 1kOhms connected to GND, ‘10’ mean 100kOhms connected to GND, ‘11’ mean high impedance"/>
48 <bitField size="2" offset="0" name="DAC_CFG" mode="3" desc="Set the two configuration bits of the DAC ‘00’ mean normal operation, ‘01’ mean 1kOhms connected to GND, ‘10’ mean 100kOhms connected to GND, ‘11’ mean high impedance"/>
45 <bitField size="1" offset="4" name="Reload" mode="3" desc="Reload freq divider to the value N, can be used also to stop dac"/>
49 <bitField size="1" offset="4" name="Reload mode enable" mode="3" desc="Reload freq divider to the value N, can be used also to stop dac"/>
46 <bitField name="Interleavde" offset="5" size="1" mode="3" desc="Set interleaved mode"/>
50 <bitField size="1" offset="5" name="Interleaved mode enable" mode="3" desc="Set interleaved mode"/>
47 <bitField name="Enable" offset="6" size="1" mode="3" desc="Scm cal enable, drives the multiplexer"/>
51 <bitField size="1" offset="6" name="DAC calibration enable" mode="3" desc="SCM CAL enable, drives the LFR CAL multiplexer"/>
52 </register>
53 <register name="DAC_PRE" addOffset="32">
54 <bitField size="8" offset="0" name="Pre" mode="3" desc="Set the prescaller division"/>
55 </register>
56 <register name="DAC_N" addOffset="36">
57 <bitField size="16" offset="0" name="N" mode="3" desc="Set the division factor"/>
58 </register>
59 <register name="DAC_ADDRESS" addOffset="40">
60 <bitField size="32" offset="0" name="DAC_ADDRESS" mode="3" desc="Set the DAC RAM buffer address pointer, auto incremented."/>
61 </register>
62 <register name="DAC_DATA" addOffset="44">
63 <bitField size="32" offset="0" name="DATA" mode="3" desc="DATA to be written in the DAC RAM buffer"/>
64 </register>
65 </peripheral>
66 <peripheral vid="25" name="LPP_LFR" pid="25">
67 <register name="SPECTRAL_MATRIX_CONFIG" addOffset="0">
68 <bitField size="1" offset="0" name="ERR_IRQ_EN" mode="3" desc="Actives interruption generation when a error occurs."/>
69 <bitField size="1" offset="1" name="COMP_IRQ_EN" mode="3" desc="Actives interruption generation when a new Matrix is completely sent in Memory."/>
70 <bitField size="1" offset="2" name="SM_EN" mode="3" desc="Enables the Spectral matrix module."/>
71 </register>
72 <register name="SPECTRAL_MATRIX_STATUS" addOffset="4">
73 <bitField size="1" offset="0" name="F0_B0_READY" mode="1" desc="Set when a matrix at f0 is ready into buffer 0."/>
74 <bitField size="1" offset="1" name="F0_B1_READY" mode="1" desc="Set when a matrix at f0 is ready into buffer 1."/>
75 <bitField size="1" offset="2" name="F1_B0_READY" mode="1" desc="Set when a matrix at f1 is ready into buffer 0."/>
76 <bitField size="1" offset="3" name="F1_B1_READY" mode="1" desc="Set when a matrix at f1 is ready into buffer 1."/>
77 <bitField size="1" offset="4" name="F2_B0_READY" mode="1" desc="Set when a matrix at f2 is ready into buffer 0."/>
78 <bitField size="1" offset="5" name="F2_B1_READY" mode="1" desc="Set when a matrix at f2 is ready into buffer 1."/>
79
80 <bitField size="1" offset="7" name="ERR_BUFFER_FULL" mode="1" desc="Set when an error “Buffer Full” occurs."/>
81 <bitField size="1" offset="8" name="ERR_FULL_FIFO0" mode="1" desc="Set when an error “write into Full FIFO_0” occurs."/>
82 <bitField size="1" offset="9" name="ERR_FULL_FIFO1" mode="1" desc="Set when an error “write into Full FIFO_1” occurs."/>
83 <bitField size="1" offset="10" name="ERR_FULL_FIFO2" mode="1" desc="Set when an error “write into Full FIFO_2” occurs."/>
84 </register>
85 <register name="SPECTRAL_MATRIX_ADDRESS_F0_0" addOffset="8">
86 <bitField size="32" offset="0" name="ADDRESS_F0_0" mode="3" desc="Base address of the first buffer where the Spectral Matrix must write the next Spectral Matrix F0."/>
87 </register>
88 <register name="SPECTRAL_MATRIX_ADDRESS_F0_1" addOffset="12">
89 <bitField size="32" offset="0" name="ADDRESS_F0_1" mode="3" desc="Base address of the second buffer where the Spectral Matrix must write the next Spectral Matrix F0."/>
90 </register>
91 <register name="SPECTRAL_MATRIX_ADDRESS_F1_0" addOffset="16">
92 <bitField size="32" offset="0" name="ADDRESS_F1_0" mode="3" desc="Base address of the first buffer where the Spectral Matrix must write the next Spectral Matrix F1."/>
93 </register>
94 <register name="SPECTRAL_MATRIX_ADDRESS_F1_1" addOffset="20">
95 <bitField size="32" offset="0" name="ADDRESS_F1_1" mode="3" desc="Base address of the second buffer where the Spectral Matrix must write the next Spectral Matrix F1."/>
96 </register>
97 <register name="SPECTRAL_MATRIX_ADDRESS_F2_0" addOffset="24">
98 <bitField size="32" offset="0" name="ADDRESS_F2_0" mode="3" desc="Base address of the first buffer where the Spectral Matrix must write the next Spectral Matrix F2."/>
99 </register>
100 <register name="SPECTRAL_MATRIX_ADDRESS_F2_1" addOffset="28">
101 <bitField size="32" offset="0" name="ADDRESS_F2_1" mode="3" desc="Base address of the second buffer where the Spectral Matrix must write the next Spectral Matrix F2."/>
48 </register>
102 </register>
49 <register name="Prescaller" addOffset="28">
103
50 <bitField size="32" offset="0" name="Pre" mode="3" desc="Set the prescaller division"/>
104 <register name="SPECTRAL_MATRIX_COARSETIME_F0_0" addOffset="32">
105 <bitField size="32" offset="0" name="COARSETIME_F0_0" mode="1" desc="CoarseTime of the first data of the first buffer Spectral Matrix F0."/>
106 </register>
107 <register name="SPECTRAL_MATRIX_FINETIME_F0_0" addOffset="36">
108 <bitField size="16" offset="0" name="FINETIME_F0_0" mode="1" desc="FineTime of the first data of the first buffer Spectral Matrix F0."/>
109 </register>
110 <register name="SPECTRAL_MATRIX_COARSETIME_F0_1" addOffset="40">
111 <bitField size="32" offset="0" name="COARSETIME_F0_1" mode="1" desc="CoarseTime of the first data of the second buffer Spectral Matrix F0."/>
112 </register>
113 <register name="SPECTRAL_MATRIX_FINETIME_F0_1" addOffset="44">
114 <bitField size="16" offset="0" name="FINETIME_F0_1" mode="1" desc="FineTime of the first data of the second buffer Spectral Matrix F0."/>
115 </register>
116
117 <register name="SPECTRAL_MATRIX_COARSETIME_F1_0" addOffset="48">
118 <bitField size="32" offset="0" name="COARSETIME_F1_0" mode="1" desc="CoarseTime of the first data of the first buffer Spectral Matrix F1."/>
119 </register>
120 <register name="SPECTRAL_MATRIX_FINETIME_F1_0" addOffset="52">
121 <bitField size="16" offset="0" name="FINETIME_F1_0" mode="1" desc="FineTime of the first data of the first buffer Spectral Matrix F1."/>
122 </register>
123 <register name="SPECTRAL_MATRIX_COARSETIME_F1_1" addOffset="56">
124 <bitField size="32" offset="0" name="COARSETIME_F1_1" mode="1" desc="CoarseTime of the first data of the second buffer Spectral Matrix F1."/>
125 </register>
126 <register name="SPECTRAL_MATRIX_FINETIME_F1_1" addOffset="60">
127 <bitField size="16" offset="0" name="FINETIME_F1_0" mode="1" desc="FineTime of the first data of the second buffer Spectral Matrix F1."/>
128 </register>
129
130 <register name="SPECTRAL_MATRIX_COARSETIME_F2_0" addOffset="64">
131 <bitField size="32" offset="0" name="COARSETIME_F2_0" mode="1" desc="CoarseTime of the first data of the first buffer Spectral Matrix F2."/>
132 </register>
133 <register name="SPECTRAL_MATRIX_FINETIME_F2_0" addOffset="68">
134 <bitField size="16" offset="0" name="FINETIME_F2_0" mode="1" desc="FineTime of the first data of the first buffer Spectral Matrix F2."/>
135 </register>
136 <register name="SPECTRAL_MATRIX_COARSETIME_F2_1" addOffset="72">
137 <bitField size="32" offset="0" name="COARSETIME_F2_1" mode="1" desc="CoarseTime of the first data of the second buffer Spectral Matrix F2."/>
138 </register>
139 <register name="SPECTRAL_MATRIX_FINETIME_F2_1" addOffset="76">
140 <bitField size="16" offset="0" name="FINETIME_F2_0" mode="1" desc="FineTime of the first data of the second buffer Spectral Matrix F2."/>
141 </register>
142
143 <register name="SPECTRAL_MATRIX_LENGTH" addOffset="80">
144 <bitField size="26" offset="0" name="LENGTH" mode="3" desc="Length of each spectral matrix buffer in 32 bit words. Length(Bytes) = LENGTH x 4."/>
145 </register>
146
147 <register name="WAVEFORM_PICKER_DATASHAPING" addOffset="84">
148 <bitField size="1" offset="0" name="BW" mode="3" desc="Set the data shaping Parameter BW."/>
149 <bitField size="1" offset="1" name="SP0" mode="3" desc="Set the data shaping Parameter SP0."/>
150 <bitField size="1" offset="2" name="SP1" mode="3" desc="Set the data shaping Parameter SP1."/>
151 <bitField size="1" offset="3" name="R0" mode="3" desc="Set the data shaping Parameter R0."/>
152 <bitField size="1" offset="4" name="R1" mode="3" desc="Set the data shaping Parameter R1."/>
153 <bitField size="1" offset="5" name="R2" mode="3" desc="Set the data shaping Parameter R2."/>
154 </register>
155
156 <register name="WAVEFORM_PICKER_CONTROL" addOffset="88">
157 <bitField size="1" offset="0" name="WF_F0_EN" mode="3" desc="Enable acquisition of Data at f0."/>
158 <bitField size="1" offset="1" name="WF_F1_EN" mode="3" desc="Enable acquisition of Data at f1."/>
159 <bitField size="1" offset="2" name="WF_F2_EN" mode="3" desc="Enable acquisition of Data at f2."/>
160 <bitField size="1" offset="3" name="WF_F3_EN" mode="3" desc="Enable acquisition of Data at f3."/>
161 <bitField size="1" offset="4" name="WF_F0_BURST_EN" mode="3" desc="Enable Burst mode for Data at f0."/>
162 <bitField size="1" offset="5" name="WF_F1_BURST_EN" mode="3" desc="Enable Burst mode for Data at f1."/>
163 <bitField size="1" offset="6" name="WF_F2_BURST_EN" mode="3" desc="Enable Burst mode for Data at f2."/>
51 </register>
164 </register>
52 <register name="Div" addOffset="32">
165
53 <bitField size="32" offset="0" name="N" mode="3" desc="Set the division factor"/>
166 <register name="WAVEFORM_PICKER_ADDRESS_F0_0" addOffset="92">
167 <bitField size="32" offset="0" name="ADDRESS_F0_0" mode="3" desc="Base address of the 1rst buffer where the Waveform Picker must write the next Data at f0."/>
168 </register>
169 <register name="WAVEFORM_PICKER_ADDRESS_F0_1" addOffset="96">
170 <bitField size="32" offset="0" name="ADDRESS_F0_1" mode="3" desc="Base address of the 2nd buffer where the Waveform Picker must write the next Data at f0."/>
171 </register>
172 <register name="WAVEFORM_PICKER_ADDRESS_F1_0" addOffset="100">
173 <bitField size="32" offset="0" name="ADDRESS_F1_0" mode="3" desc="Base address of the 1rst buffer where the Waveform Picker must write the next Data at f1."/>
174 </register>
175 <register name="WAVEFORM_PICKER_ADDRESS_F1_1" addOffset="104">
176 <bitField size="32" offset="0" name="ADDRESS_F1_1" mode="3" desc="Base address of the 2nd buffer where the Waveform Picker must write the next Data at f1."/>
177 </register>
178 <register name="WAVEFORM_PICKER_ADDRESS_F2_0" addOffset="108">
179 <bitField size="32" offset="0" name="ADDRESS_F2_0" mode="3" desc="Base address of the 1rst buffer where the Waveform Picker must write the next Data at f2."/>
180 </register>
181 <register name="WAVEFORM_PICKER_ADDRESS_F2_1" addOffset="112">
182 <bitField size="32" offset="0" name="ADDRESS_F2_1" mode="3" desc="Base address of the 2nd buffer where the Waveform Picker must write the next Data at f2."/>
183 </register>
184 <register name="WAVEFORM_PICKER_ADDRESS_F3_0" addOffset="116">
185 <bitField size="32" offset="0" name="ADDRESS_F3_0" mode="3" desc="Base address of the 1rst buffer where the Waveform Picker must write the next Data at f3."/>
186 </register>
187 <register name="WAVEFORM_PICKER_ADDRESS_F3_1" addOffset="120">
188 <bitField size="32" offset="0" name="ADDRESS_F3_1" mode="3" desc="Base address of the 2nd buffer where the Waveform Picker must write the next Data at f3."/>
189 </register>
190
191 <register name="WAVEFORM_PICKER_STATUS" addOffset="124">
192 <bitField size="8" offset="0" name="FULL" mode="1" desc="Vector of Full Status bits for each data buffer f0_0 to f3_1. Set when Waveform Buffer of Data is full. Each bit is automatically cleared after read."/>
193 <bitField size="4" offset="8" name="ERR_FULL" mode="1" desc="Vector of Full Error bits for Data buffer f0_0 to.f3_0. The bit 0 is for full error of data f0_0, etc. Set when Waveform Buffer of Data is full and that a new data should be writing. Those bits are automatically cleared after read."/>
194 <bitField size="4" offset="12" name="ERR_NEW" mode="1" desc="Vector of New Error bits for Data f0 to f3. The bit 0 is for new error of data f0, etc. Set when internal buffer (FIFO) is full and a new data should be writing. Those bits are automatically reset after read."/>
195 </register>
196 <register name="WAVEFORM_PICKER_DELTASNAPSHOT" addOffset="128">
197 <bitField size="32" offset="0" name="DELTASNAPSHOT" mode="3" desc="DeltaSnapshot parameter."/>
198 </register>
199 <register name="WAVEFORM_PICKER_DELTA_f0" addOffset="132">
200 <bitField size="32" offset="0" name="DELTA_f0" mode="3" desc="Delta_f0 parameter."/>
201 </register>
202 <register name="WAVEFORM_PICKER_DELTA_f0_2" addOffset="136">
203 <bitField size="7" offset="0" name="DELTA_f0_2" mode="3" desc="Delta_f0_2 parameter."/>
204 </register>
205 <register name="WAVEFORM_PICKER_DELTA_f1" addOffset="140">
206 <bitField size="32" offset="0" name="DELTA_f1" mode="3" desc="Delta_f1 parameter."/>
207 </register>
208 <register name="WAVEFORM_PICKER_DELTA_f2" addOffset="144">
209 <bitField size="32" offset="0" name="DELTA_f2" mode="3" desc="Delta_f2 parameter."/>
210 </register>
211 <register name="WAVEFORM_PICKER_NBDATABYBUFFER" addOffset="148">
212 <bitField size="32" offset="0" name="NBDATABYBUFFER" mode="3" desc="Number of data by buffer (one data is 6*2B)."/>
213 </register>
214 <register name="WAVEFORM_PICKER_NBSNAPSHOT" addOffset="152">
215 <bitField size="32" offset="0" name="FULL" mode="3" desc="Nb_snapshot_param parameter."/>
216 </register>
217 <register name="WAVEFORM_PICKER_START_DATE" addOffset="156">
218 <bitField size="32" offset="0" name="START_DATE" mode="3" desc="The start date. When this date is equal or lesser than the time management date, the waveform starts"/>
219 </register>
220
221 <register name="WAVEFORM_PICKER_COARSETIME_F0_0" addOffset="160">
222 <bitField size="32" offset="0" name="COARSETIME_F0_0" mode="1" desc="CoarseTime of the first data of the first WaveFormPicker buffer F0."/>
223 </register>
224 <register name="WAVEFORM_PICKER_FINETIME_F0_0" addOffset="164">
225 <bitField size="16" offset="0" name="FINETIME_F0_0" mode="1" desc="FineTime of the first data of the first WaveFormPicker buffer F0."/>
54 </register>
226 </register>
55 <register name="Address" addOffset="36">
227 <register name="WAVEFORM_PICKER_COARSETIME_F0_1" addOffset="168">
56 <bitField size="32" offset="0" name="Address" mode="3" desc="Set the DAC RAM buffer address pointer"/>
228 <bitField size="32" offset="0" name="COARSETIME_F0_1" mode="1" desc="CoarseTime of the first data of the 2nd WaveFormPicker buffer F0."/>
229 </register>
230 <register name="WAVEFORM_PICKER_FINETIME_F0_1" addOffset="172">
231 <bitField size="32" offset="0" name="FINETIME_F0_1" mode="1" desc="CoarseTime of the first data of the 2nd WaveFormPicker buffer F0."/>
232 </register>
233
234 <register name="WAVEFORM_PICKER_COARSETIME_F1_0" addOffset="176">
235 <bitField size="32" offset="0" name="COARSETIME_F1_0" mode="1" desc="CoarseTime of the first data of the first WaveFormPicker buffer F1."/>
236 </register>
237 <register name="WAVEFORM_PICKER_FINETIME_F1_0" addOffset="180">
238 <bitField size="16" offset="0" name="FINETIME_F1_0" mode="1" desc="FineTime of the first data of the first WaveFormPicker buffer F1."/>
239 </register>
240 <register name="WAVEFORM_PICKER_COARSETIME_F1_1" addOffset="184">
241 <bitField size="32" offset="0" name="COARSETIME_F1_1" mode="1" desc="CoarseTime of the first data of the 2nd WaveFormPicker buffer F1."/>
242 </register>
243 <register name="WAVEFORM_PICKER_FINETIME_F1_1" addOffset="188">
244 <bitField size="32" offset="0" name="FINETIME_F1_1" mode="1" desc="CoarseTime of the first data of the 2nd WaveFormPicker buffer F1."/>
245 </register>
246
247 <register name="WAVEFORM_PICKER_COARSETIME_F2_0" addOffset="192">
248 <bitField size="32" offset="0" name="COARSETIME_F2_0" mode="1" desc="CoarseTime of the first data of the first WaveFormPicker buffer F2."/>
249 </register>
250 <register name="WAVEFORM_PICKER_FINETIME_F2_0" addOffset="196">
251 <bitField size="16" offset="0" name="FINETIME_F2_0" mode="1" desc="FineTime of the first data of the first WaveFormPicker buffer F2."/>
252 </register>
253 <register name="WAVEFORM_PICKER_COARSETIME_F2_1" addOffset="200">
254 <bitField size="32" offset="0" name="COARSETIME_F2_1" mode="1" desc="CoarseTime of the first data of the 2nd WaveFormPicker buffer F2."/>
57 </register>
255 </register>
58 <register name="DATA" addOffset="40">
256 <register name="WAVEFORM_PICKER_FINETIME_F2_1" addOffset="204">
59 <bitField size="32" offset="0" name="DATA" mode="3" desc="DATA to be written in the DAC RAM buffer"/>
257 <bitField size="32" offset="0" name="FINETIME_F2_1" mode="1" desc="CoarseTime of the first data of the 2nd WaveFormPicker buffer F2."/>
258 </register>
259
260 <register name="WAVEFORM_PICKER_COARSETIME_F3_0" addOffset="208">
261 <bitField size="32" offset="0" name="COARSETIME_F3_0" mode="1" desc="CoarseTime of the first data of the first WaveFormPicker buffer F3."/>
262 </register>
263 <register name="WAVEFORM_PICKER_FINETIME_F3_0" addOffset="212">
264 <bitField size="16" offset="0" name="FINETIME_F3_0" mode="1" desc="FineTime of the first data of the first WaveFormPicker buffer F3."/>
265 </register>
266 <register name="WAVEFORM_PICKER_COARSETIME_F3_1" addOffset="216">
267 <bitField size="32" offset="0" name="COARSETIME_F3_1" mode="1" desc="CoarseTime of the first data of the 2nd WaveFormPicker buffer F3."/>
268 </register>
269 <register name="WAVEFORM_PICKER_FINETIME_F3_1" addOffset="220">
270 <bitField size="32" offset="0" name="FINETIME_F3_1" mode="1" desc="CoarseTime of the first data of the 2nd WaveFormPicker buffer F3."/>
271 </register>
272
273 <register name="WAVEFORM_PICKER_BUFFER_LENGTH" addOffset="224">
274 <bitField size="26" offset="0" name="BUFFER_LENGTH" mode="3" desc="Nb_word_by_buffer parameter. Indicates the buffer’s size in words (4B)."/>
275 </register>
276 <register name="V_F3" addOffset="228">
277 <bitField size="16" offset="0" name="V_F3" mode="3" desc="Current V value (from F3 channel)."/>
278 </register>
279 <register name="E1_F3" addOffset="232">
280 <bitField size="16" offset="0" name="E1_F3" mode="3" desc="Current E1 value (from F3 channel)."/>
281 </register>
282 <register name="E2_F3" addOffset="236">
283 <bitField size="16" offset="0" name="E2_F3" mode="3" desc="Current E2 value (from F3 channel)."/>
284 </register>
285 <register name="LFR_RTL_VERSION" addOffset="240">
286 <bitField size="8" offset="0" name="MINOR" mode="3" desc="Minor version."/>
287 <bitField size="8" offset="8" name="MAJOR" mode="3" desc="Major version."/>
288 <bitField size="8" offset="16" name="BOARD" mode="3" desc="Current board&#xa;0 => mini-LFR&#xa;1 => LFR-em&#xa;2 => LFR-EQM with A3PE3000L FPGA&#xa;3 => LFR-EQM/FM with RTAX FPGA"/>
60 </register>
289 </register>
61 </peripheral>
290 </peripheral>
62 </soc>
291 </soc>
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