@@ -1,2 +1,2 | |||||
1 | 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters |
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1 | 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters | |
2 | d4a9a4d748d56d86427bfe03a6777fae4cfe3ae1 header/lfr_common_headers |
|
2 | 7c46de6059673d3239fcc7103e16510727f35923 header/lfr_common_headers |
@@ -119,6 +119,8 typedef struct { | |||||
119 | #define BIT_WFP_BUFFER_1 0x02 |
|
119 | #define BIT_WFP_BUFFER_1 0x02 | |
120 |
|
120 | |||
121 | #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0 |
|
121 | #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0 | |
|
122 | #define BITS_WFP_ENABLE_ALL 0x0f // [0000 1111] enable f3, f2, f1, f0 | |||
|
123 | #define BITS_WFP_ENABLE_BURST 0x0c // [0000 1100] enable f3, f2 | |||
122 | #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst |
|
124 | #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst | |
123 | #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled |
|
125 | #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled | |
124 |
|
126 |
@@ -15,6 +15,15 | |||||
15 | #define MAX_SRC_DATA 780 // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1] |
|
15 | #define MAX_SRC_DATA 780 // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1] | |
16 | #define MAX_SRC_DATA_WITH_SPARE 143 // 13 bins * 11 Bytes |
|
16 | #define MAX_SRC_DATA_WITH_SPARE 143 // 13 bins * 11 Bytes | |
17 |
|
17 | |||
|
18 | #define NODE_0 0 | |||
|
19 | #define NODE_1 1 | |||
|
20 | #define NODE_2 2 | |||
|
21 | #define NODE_3 3 | |||
|
22 | #define NODE_4 4 | |||
|
23 | #define NODE_5 5 | |||
|
24 | #define NODE_6 6 | |||
|
25 | #define NODE_7 7 | |||
|
26 | ||||
18 | typedef struct ring_node_asm |
|
27 | typedef struct ring_node_asm | |
19 | { |
|
28 | { | |
20 | struct ring_node_asm *next; |
|
29 | struct ring_node_asm *next; | |
@@ -205,14 +214,14 void SM_average( float *averaged_spec_ma | |||||
205 | // + ( (int *) (ring_node_tab[6]->buffer_address) ) [ i ] |
|
214 | // + ( (int *) (ring_node_tab[6]->buffer_address) ) [ i ] | |
206 | // + ( (int *) (ring_node_tab[7]->buffer_address) ) [ i ]; |
|
215 | // + ( (int *) (ring_node_tab[7]->buffer_address) ) [ i ]; | |
207 |
|
216 | |||
208 | sum = ( incomingSMIsValid[0] * ((int *)(ring_node_tab[0]->buffer_address) )[ i ] ) |
|
217 | sum = ( incomingSMIsValid[BYTE_0] * ((int *)(ring_node_tab[NODE_0]->buffer_address) )[ i ] ) | |
209 | + ( incomingSMIsValid[1] * ((int *)(ring_node_tab[1]->buffer_address) )[ i ] ) |
|
218 | + ( incomingSMIsValid[BYTE_1] * ((int *)(ring_node_tab[NODE_1]->buffer_address) )[ i ] ) | |
210 | + ( incomingSMIsValid[2] * ((int *)(ring_node_tab[2]->buffer_address) )[ i ] ) |
|
219 | + ( incomingSMIsValid[BYTE_2] * ((int *)(ring_node_tab[NODE_2]->buffer_address) )[ i ] ) | |
211 | + ( incomingSMIsValid[3] * ((int *)(ring_node_tab[3]->buffer_address) )[ i ] ) |
|
220 | + ( incomingSMIsValid[BYTE_3] * ((int *)(ring_node_tab[NODE_3]->buffer_address) )[ i ] ) | |
212 | + ( incomingSMIsValid[4] * ((int *)(ring_node_tab[4]->buffer_address) )[ i ] ) |
|
221 | + ( incomingSMIsValid[BYTE_4] * ((int *)(ring_node_tab[NODE_4]->buffer_address) )[ i ] ) | |
213 | + ( incomingSMIsValid[5] * ((int *)(ring_node_tab[5]->buffer_address) )[ i ] ) |
|
222 | + ( incomingSMIsValid[BYTE_5] * ((int *)(ring_node_tab[NODE_5]->buffer_address) )[ i ] ) | |
214 | + ( incomingSMIsValid[6] * ((int *)(ring_node_tab[6]->buffer_address) )[ i ] ) |
|
223 | + ( incomingSMIsValid[BYTE_6] * ((int *)(ring_node_tab[NODE_6]->buffer_address) )[ i ] ) | |
215 | + ( incomingSMIsValid[7] * ((int *)(ring_node_tab[7]->buffer_address) )[ i ] ); |
|
224 | + ( incomingSMIsValid[BYTE_7] * ((int *)(ring_node_tab[NODE_7]->buffer_address) )[ i ] ); | |
216 |
|
225 | |||
217 | if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) ) |
|
226 | if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) ) | |
218 | { |
|
227 | { |
@@ -85,7 +85,7 unsigned short sequenceCounters_SCIENCE_ | |||||
85 | unsigned short sequenceCounters_SCIENCE_SBM1_SBM2 = 0; |
|
85 | unsigned short sequenceCounters_SCIENCE_SBM1_SBM2 = 0; | |
86 | unsigned short sequenceCounters_TC_EXE[SEQ_CNT_NB_DEST_ID] = {0}; |
|
86 | unsigned short sequenceCounters_TC_EXE[SEQ_CNT_NB_DEST_ID] = {0}; | |
87 | unsigned short sequenceCounters_TM_DUMP[SEQ_CNT_NB_DEST_ID] = {0}; |
|
87 | unsigned short sequenceCounters_TM_DUMP[SEQ_CNT_NB_DEST_ID] = {0}; | |
88 | unsigned short sequenceCounterHK; |
|
88 | unsigned short sequenceCounterHK = {0}; | |
89 | spw_stats grspw_stats = {0}; |
|
89 | spw_stats grspw_stats = {0}; | |
90 |
|
90 | |||
91 | // TC_LFR_UPDATE_INFO |
|
91 | // TC_LFR_UPDATE_INFO |
@@ -349,9 +349,9 rtems_task avgv_task(rtems_task_argument | |||||
349 | { |
|
349 | { | |
350 | #define MOVING_AVERAGE 16 |
|
350 | #define MOVING_AVERAGE 16 | |
351 | rtems_status_code status; |
|
351 | rtems_status_code status; | |
352 | unsigned int v[MOVING_AVERAGE]; |
|
352 | static unsigned int v[MOVING_AVERAGE] = {0}; | |
353 | unsigned int e1[MOVING_AVERAGE]; |
|
353 | static unsigned int e1[MOVING_AVERAGE] = {0}; | |
354 | unsigned int e2[MOVING_AVERAGE]; |
|
354 | static unsigned int e2[MOVING_AVERAGE] = {0}; | |
355 | float average_v; |
|
355 | float average_v; | |
356 | float average_e1; |
|
356 | float average_e1; | |
357 | float average_e2; |
|
357 | float average_e2; | |
@@ -376,17 +376,10 rtems_task avgv_task(rtems_task_argument | |||||
376 | } |
|
376 | } | |
377 |
|
377 | |||
378 | // initialize values |
|
378 | // initialize values | |
379 | k = 0; |
|
|||
380 | indexOfOldValue = MOVING_AVERAGE - 1; |
|
379 | indexOfOldValue = MOVING_AVERAGE - 1; | |
381 | for (k = 0; k < MOVING_AVERAGE; k++) |
|
380 | average_v = 0.; | |
382 | { |
|
381 | average_e1 = 0.; | |
383 | v[k] = 0; |
|
382 | average_e2 = 0.; | |
384 | e1[k] = 0; |
|
|||
385 | e2[k] = 0; |
|
|||
386 | average_v = 0.; |
|
|||
387 | average_e1 = 0.; |
|
|||
388 | average_e2 = 0.; |
|
|||
389 | } |
|
|||
390 |
|
383 | |||
391 | k = 0; |
|
384 | k = 0; | |
392 |
|
385 | |||
@@ -793,7 +786,7 void increment_hk_counter( unsigned char | |||||
793 | } |
|
786 | } | |
794 | else |
|
787 | else | |
795 | { |
|
788 | { | |
796 | delta = 255 - oldValue + newValue; |
|
789 | delta = (255 - oldValue) + newValue; | |
797 | } |
|
790 | } | |
798 |
|
791 | |||
799 | *counter = *counter + delta; |
|
792 | *counter = *counter + delta; | |
@@ -906,7 +899,7 void hk_lfr_le_me_he_update() | |||||
906 |
|
899 | |||
907 | unsigned int hk_lfr_he_cnt; |
|
900 | unsigned int hk_lfr_he_cnt; | |
908 |
|
901 | |||
909 | hk_lfr_he_cnt = ((unsigned int) housekeeping_packet.hk_lfr_he_cnt[0]) * 256 + housekeeping_packet.hk_lfr_he_cnt[1]; |
|
902 | hk_lfr_he_cnt = (((unsigned int) housekeeping_packet.hk_lfr_he_cnt[0]) * 256) + housekeeping_packet.hk_lfr_he_cnt[1]; | |
910 |
|
903 | |||
911 | //update the low severity error counter |
|
904 | //update the low severity error counter | |
912 | hk_lfr_le_update( ); |
|
905 | hk_lfr_le_update( ); |
@@ -43,4 +43,6 float K55_pe = 1; | |||||
43 | float K45_pe_re = 1; |
|
43 | float K45_pe_re = 1; | |
44 | float K45_pe_im = 1; |
|
44 | float K45_pe_im = 1; | |
45 |
|
45 | |||
46 | float Alpha_M = M_PI/4; |
|
46 | #define ALPHA_M (M_PI / 4) | |
|
47 | ||||
|
48 | float Alpha_M = ALPHA_M; |
@@ -675,7 +675,9 void spacewire_get_last_error( void ) | |||||
675 | unsigned char update_hk_lfr_last_er; |
|
675 | unsigned char update_hk_lfr_last_er; | |
676 |
|
676 | |||
677 | memset(¤t, 0, sizeof(spw_stats)); |
|
677 | memset(¤t, 0, sizeof(spw_stats)); | |
678 |
|
|
678 | hk_lfr_last_er_rid = INIT_CHAR; | |
|
679 | hk_lfr_last_er_code = INIT_CHAR; | |||
|
680 | update_hk_lfr_last_er = INIT_CHAR; | |||
679 |
|
681 | |||
680 | status = ioctl( fdSPW, SPACEWIRE_IOCTRL_GET_STATISTICS, ¤t ); |
|
682 | status = ioctl( fdSPW, SPACEWIRE_IOCTRL_GET_STATISTICS, ¤t ); | |
681 |
|
683 |
@@ -693,7 +693,7 int getFBinMask( int index, unsigned cha | |||||
693 | int fbin; |
|
693 | int fbin; | |
694 | unsigned char *sy_lfr_fbins_fx_word1; |
|
694 | unsigned char *sy_lfr_fbins_fx_word1; | |
695 |
|
695 | |||
696 |
sy_lfr_fbins_fx_word1 = parameter_dump_packet.sy_lfr_fbins |
|
696 | sy_lfr_fbins_fx_word1 = parameter_dump_packet.sy_lfr_fbins_f0_word1; | |
697 |
|
697 | |||
698 | switch(channel) |
|
698 | switch(channel) | |
699 | { |
|
699 | { | |
@@ -793,9 +793,9 void init_kcoeff_sbm_from_kcoeff_norm(fl | |||||
793 | { |
|
793 | { | |
794 | for (kcoeff=0; kcoeff<NB_K_COEFF_PER_BIN; kcoeff++) |
|
794 | for (kcoeff=0; kcoeff<NB_K_COEFF_PER_BIN; kcoeff++) | |
795 | { |
|
795 | { | |
796 |
output_kcoeff[ ( ( |
|
796 | output_kcoeff[ ( (bin * NB_K_COEFF_PER_BIN) + kcoeff ) * SBM_COEFF_PER_NORM_COEFF ] | |
797 | = input_kcoeff[ (bin*NB_K_COEFF_PER_BIN) + kcoeff ]; |
|
797 | = input_kcoeff[ (bin*NB_K_COEFF_PER_BIN) + kcoeff ]; | |
798 |
output_kcoeff[ ( ( bin * NB_K_COEFF_PER_BIN ) + kcoeff |
|
798 | output_kcoeff[ ( ( (bin * NB_K_COEFF_PER_BIN ) + kcoeff) * SBM_COEFF_PER_NORM_COEFF ) + 1 ] | |
799 | = input_kcoeff[ (bin*NB_K_COEFF_PER_BIN) + kcoeff ]; |
|
799 | = input_kcoeff[ (bin*NB_K_COEFF_PER_BIN) + kcoeff ]; | |
800 | } |
|
800 | } | |
801 | } |
|
801 | } |
@@ -1096,15 +1096,15 void build_sy_lfr_rw_mask( unsigned int | |||||
1096 | switch (channel) |
|
1096 | switch (channel) | |
1097 | { |
|
1097 | { | |
1098 | case CHANNELF0: |
|
1098 | case CHANNELF0: | |
1099 |
maskPtr = parameter_dump_packet.sy_lfr_rw_mask |
|
1099 | maskPtr = parameter_dump_packet.sy_lfr_rw_mask_f0_word1; | |
1100 | deltaF = DELTAF_F0; |
|
1100 | deltaF = DELTAF_F0; | |
1101 | break; |
|
1101 | break; | |
1102 | case CHANNELF1: |
|
1102 | case CHANNELF1: | |
1103 |
maskPtr = parameter_dump_packet.sy_lfr_rw_mask |
|
1103 | maskPtr = parameter_dump_packet.sy_lfr_rw_mask_f1_word1; | |
1104 | deltaF = DELTAF_F1; |
|
1104 | deltaF = DELTAF_F1; | |
1105 | break; |
|
1105 | break; | |
1106 | case CHANNELF2: |
|
1106 | case CHANNELF2: | |
1107 |
maskPtr = parameter_dump_packet.sy_lfr_rw_mask |
|
1107 | maskPtr = parameter_dump_packet.sy_lfr_rw_mask_f2_word1; | |
1108 | deltaF = DELTAF_F2; |
|
1108 | deltaF = DELTAF_F2; | |
1109 | break; |
|
1109 | break; | |
1110 | default: |
|
1110 | default: | |
@@ -1168,12 +1168,12 void merge_fbins_masks( void ) | |||||
1168 | unsigned char *rw_mask_f1; |
|
1168 | unsigned char *rw_mask_f1; | |
1169 | unsigned char *rw_mask_f2; |
|
1169 | unsigned char *rw_mask_f2; | |
1170 |
|
1170 | |||
1171 |
fbins_f0 = parameter_dump_packet.sy_lfr_fbins |
|
1171 | fbins_f0 = parameter_dump_packet.sy_lfr_fbins_f0_word1; | |
1172 |
fbins_f1 = parameter_dump_packet.sy_lfr_fbins |
|
1172 | fbins_f1 = parameter_dump_packet.sy_lfr_fbins_f1_word1; | |
1173 |
fbins_f2 = parameter_dump_packet.sy_lfr_fbins |
|
1173 | fbins_f2 = parameter_dump_packet.sy_lfr_fbins_f2_word1; | |
1174 |
rw_mask_f0 = parameter_dump_packet.sy_lfr_rw_mask |
|
1174 | rw_mask_f0 = parameter_dump_packet.sy_lfr_rw_mask_f0_word1; | |
1175 |
rw_mask_f1 = parameter_dump_packet.sy_lfr_rw_mask |
|
1175 | rw_mask_f1 = parameter_dump_packet.sy_lfr_rw_mask_f1_word1; | |
1176 |
rw_mask_f2 = parameter_dump_packet.sy_lfr_rw_mask |
|
1176 | rw_mask_f2 = parameter_dump_packet.sy_lfr_rw_mask_f2_word1; | |
1177 |
|
1177 | |||
1178 | for( k=0; k < BYTES_PER_MASK; k++ ) |
|
1178 | for( k=0; k < BYTES_PER_MASK; k++ ) | |
1179 | { |
|
1179 | { | |
@@ -1195,7 +1195,7 int set_sy_lfr_fbins( ccsdsTelecommandPa | |||||
1195 |
|
1195 | |||
1196 | status = LFR_SUCCESSFUL; |
|
1196 | status = LFR_SUCCESSFUL; | |
1197 |
|
1197 | |||
1198 |
fbins_mask_dump = parameter_dump_packet.sy_lfr_fbins |
|
1198 | fbins_mask_dump = parameter_dump_packet.sy_lfr_fbins_f0_word1; | |
1199 | fbins_mask_TC = TC->dataAndCRC; |
|
1199 | fbins_mask_TC = TC->dataAndCRC; | |
1200 |
|
1200 | |||
1201 | for (k=0; k < BYTES_PER_MASKS_SET; k++) |
|
1201 | for (k=0; k < BYTES_PER_MASKS_SET; k++) | |
@@ -1490,7 +1490,7 void init_parameter_dump( void ) | |||||
1490 | // FBINS MASKS |
|
1490 | // FBINS MASKS | |
1491 | for (k=0; k < BYTES_PER_MASKS_SET; k++) |
|
1491 | for (k=0; k < BYTES_PER_MASKS_SET; k++) | |
1492 | { |
|
1492 | { | |
1493 |
parameter_dump_packet.sy_lfr_fbins |
|
1493 | parameter_dump_packet.sy_lfr_fbins_f0_word1[k] = INT8_ALL_F; | |
1494 | } |
|
1494 | } | |
1495 |
|
1495 | |||
1496 | // PAS FILTER PARAMETERS |
|
1496 | // PAS FILTER PARAMETERS | |
@@ -1505,7 +1505,7 void init_parameter_dump( void ) | |||||
1505 | // LFR_RW_MASK |
|
1505 | // LFR_RW_MASK | |
1506 | for (k=0; k < BYTES_PER_MASKS_SET; k++) |
|
1506 | for (k=0; k < BYTES_PER_MASKS_SET; k++) | |
1507 | { |
|
1507 | { | |
1508 |
parameter_dump_packet.sy_lfr_rw_mask |
|
1508 | parameter_dump_packet.sy_lfr_rw_mask_f0_word1[k] = INT8_ALL_F; | |
1509 | } |
|
1509 | } | |
1510 |
|
1510 | |||
1511 | // once the reaction wheels masks have been initialized, they have to be merged with the fbins masks |
|
1511 | // once the reaction wheels masks have been initialized, they have to be merged with the fbins masks |
@@ -208,7 +208,7 inline void waveform_isr_normal_sbm1_sbm | |||||
208 |
|
208 | |||
209 | //*** |
|
209 | //*** | |
210 | // F1 |
|
210 | // F1 | |
211 |
if ( (waveform_picker_regs->status & |
|
211 | if ( (waveform_picker_regs->status & BITS_WFP_STATUS_F1) != INIT_CHAR ) { // [0000 1100] check the f1 full bits | |
212 | // (1) change the receiving buffer for the waveform picker |
|
212 | // (1) change the receiving buffer for the waveform picker | |
213 | ring_node_to_send_cwf_f1 = current_ring_node_f1->previous; |
|
213 | ring_node_to_send_cwf_f1 = current_ring_node_f1->previous; | |
214 | current_ring_node_f1 = current_ring_node_f1->next; |
|
214 | current_ring_node_f1 = current_ring_node_f1->next; | |
@@ -1167,11 +1167,11 void set_wfp_burst_enable_register( unsi | |||||
1167 | case LFR_MODE_SBM1: |
|
1167 | case LFR_MODE_SBM1: | |
1168 | case LFR_MODE_SBM2: |
|
1168 | case LFR_MODE_SBM2: | |
1169 | waveform_picker_regs->run_burst_enable = RUN_BURST_ENABLE_SBM2; // [0110 0000] enable f2 and f1 burst |
|
1169 | waveform_picker_regs->run_burst_enable = RUN_BURST_ENABLE_SBM2; // [0110 0000] enable f2 and f1 burst | |
1170 |
waveform_picker_regs->run_burst_enable = waveform_picker_regs->run_burst_enable | |
|
1170 | waveform_picker_regs->run_burst_enable = waveform_picker_regs->run_burst_enable | BITS_WFP_ENABLE_ALL; // [1111] enable f3 f2 f1 f0 | |
1171 | break; |
|
1171 | break; | |
1172 | case LFR_MODE_BURST: |
|
1172 | case LFR_MODE_BURST: | |
1173 | waveform_picker_regs->run_burst_enable = RUN_BURST_ENABLE_BURST; // [0100 0000] f2 burst enabled |
|
1173 | waveform_picker_regs->run_burst_enable = RUN_BURST_ENABLE_BURST; // [0100 0000] f2 burst enabled | |
1174 |
waveform_picker_regs->run_burst_enable = waveform_picker_regs->run_burst_enable | |
|
1174 | waveform_picker_regs->run_burst_enable = waveform_picker_regs->run_burst_enable | BITS_WFP_ENABLE_BURST; // [1100] enable f3 and f2 | |
1175 | break; |
|
1175 | break; | |
1176 | default: |
|
1176 | default: | |
1177 | waveform_picker_regs->run_burst_enable = INIT_CHAR; // [0000 0000] no burst enabled, no waveform enabled |
|
1177 | waveform_picker_regs->run_burst_enable = INIT_CHAR; // [0000 0000] no burst enabled, no waveform enabled |
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