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Clone from http://pc-instru.lpp.polytechnique.fr:5000/DEV_PLE

EDAC information fetching functions added.
paul -
r251:b70f1b89bd70 R3a
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@@ -1,7 +1,15
1 TEMPLATE = app
1 TEMPLATE = app
2 # CONFIG += console v8 sim
2 # CONFIG += console v8 sim
3 # CONFIG options = verbose *** boot_messages *** debug_messages *** cpu_usage_report *** stack_report *** vhdl_dev *** debug_tch
3 # CONFIG options =
4 # lpp_dpu_destid
4 # verbose
5 # boot_messages
6 # debug_messages
7 # cpu_usage_report
8 # stack_report
9 # vhdl_dev
10 # debug_tch
11 # lpp_dpu_destid REMOVE BEFORE DELIVERY TO LESIA
12 # debug_watchdog
5 CONFIG += console verbose lpp_dpu_destid
13 CONFIG += console verbose lpp_dpu_destid
6 CONFIG -= qt
14 CONFIG -= qt
7
15
@@ -12,7 +20,7 SWVERSION=-1-0
12 DEFINES += SW_VERSION_N1=3 # major
20 DEFINES += SW_VERSION_N1=3 # major
13 DEFINES += SW_VERSION_N2=0 # minor
21 DEFINES += SW_VERSION_N2=0 # minor
14 DEFINES += SW_VERSION_N3=0 # patch
22 DEFINES += SW_VERSION_N3=0 # patch
15 DEFINES += SW_VERSION_N4=13 # internal
23 DEFINES += SW_VERSION_N4=14 # internal
16
24
17 # <GCOV>
25 # <GCOV>
18 #QMAKE_CFLAGS_RELEASE += -fprofile-arcs -ftest-coverage
26 #QMAKE_CFLAGS_RELEASE += -fprofile-arcs -ftest-coverage
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@@ -5,65 +5,188
5 #define LEON3
5 #define LEON3
6 #endif
6 #endif
7
7
8 static unsigned int getCacheControlRegister(){
8 #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
9 #ifdef LEON3
9 #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
10 unsigned int cacheControlRegister = 0;
10
11 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
11 #define DEVICEID_LEON3 0x003
12 return cacheControlRegister;
12 #define DEVICEID_LEON3FT 0x053
13 #endif
13 #define VENDORID_GAISLER 0x01
14 }
15
14
16 static void setCacheControlRegister(unsigned int cacheControlRegister)
15 // CCR
16 #define POS_ITE 12
17 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
18 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
19 #define POS_IDE 10
20 #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
21 #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
22 //
23 #define POS_DTE 8
24 #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
25 #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
26 #define POS_DDE 6
27 #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
28 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
29
30 // ASR16
31 #define POS_FPRF 27
32 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
33 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
34 #define POS_IURF 11
35 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
36 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
37
38 volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
39
40 static inline void flushCache()
17 {
41 {
18 #ifdef LEON3
42 /**
19 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
43 * Flush the data cache and the instruction cache.
20 #endif
44 *
21 }
45 * @param void
22
46 *
47 * @return void
48 */
23
49
24 /**
25 * Flush the data cache and the instruction cache.
26 *
27 * @return
28 */
29 static inline void flushCache() {
30 asm("flush");
50 asm("flush");
31 }
51 }
32
52
33 static void resetCacheControlRegister() {
53 //***************************
34 #ifdef LEON3
54 // CCR Cache control register
55
56 static unsigned int CCR_getValue()
57 {
58 unsigned int cacheControlRegister = 0;
59 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
60 return cacheControlRegister;
61 }
62
63 static void CCR_setValue(unsigned int cacheControlRegister)
64 {
65 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
66 }
67
68 static void CCR_resetCacheControlRegister()
69 {
35 unsigned int cacheControlRegister;
70 unsigned int cacheControlRegister;
36 cacheControlRegister = 0x00;
71 cacheControlRegister = 0x00;
37 setCacheControlRegister(cacheControlRegister);
72 CCR_setValue(cacheControlRegister);
38 #endif
73 }
74
75 static void CCR_enableInstructionCache()
76 {
77 // [1:0] Instruction Cache state (ICS)
78 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
79 unsigned int cacheControlRegister;
80 cacheControlRegister = CCR_getValue();
81 cacheControlRegister = (cacheControlRegister | 0x3);
82 CCR_setValue(cacheControlRegister);
39 }
83 }
40
84
41 static void enableInstructionCache() {
85 static void CCR_enableDataCache()
42 #ifdef LEON3
86 {
87 // [3:2] Data Cache state (DCS)
88 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
89 unsigned int cacheControlRegister;
90 cacheControlRegister = CCR_getValue();
91 cacheControlRegister = (cacheControlRegister | 0xc);
92 CCR_setValue(cacheControlRegister);
93 }
94
95 static void CCR_faultTolerantScheme()
96 {
97 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
43 unsigned int cacheControlRegister;
98 unsigned int cacheControlRegister;
44 cacheControlRegister = getCacheControlRegister();
99 unsigned int *plugAndPlayRegister;
45 cacheControlRegister = (cacheControlRegister | 0x3);
100 unsigned int vendorId;
46 setCacheControlRegister(cacheControlRegister);
101 unsigned int deviceId;
47 #endif
102
103 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
104 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
105 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
106
107 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
108 {
109 PRINTF("in faultTolerantScheme *** Leon3FT detected, configure the CCR FT bits");
110 cacheControlRegister = CCR_getValue();
111 cacheControlRegister = (cacheControlRegister | 0xc);
112 CCR_setValue(cacheControlRegister);
113 }
114 else
115 {
116 PRINTF("in faultTolerantScheme *** not a Leon3FT, no need to configure the CCR FT bits\n");
117 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
118 }
48 }
119 }
49
120
50 static void enableDataCache() {
121 static void CCR_enableInstructionBurstFetch()
51 #ifdef LEON3
122 {
123 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
52 unsigned int cacheControlRegister;
124 unsigned int cacheControlRegister;
53 cacheControlRegister = getCacheControlRegister();
125 cacheControlRegister = CCR_getValue();
54 cacheControlRegister = (cacheControlRegister | 0xc);
126 // set the bit IB to 1
55 setCacheControlRegister(cacheControlRegister);
127 cacheControlRegister = (cacheControlRegister | 0x10000);
56 #endif
128 CCR_setValue(cacheControlRegister);
57 }
129 }
58
130
59 static void enableInstructionBurstFetch() {
131 static void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
60 #ifdef LEON3
132 {
133 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
134 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
135 // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
136 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
137
61 unsigned int cacheControlRegister;
138 unsigned int cacheControlRegister;
62 cacheControlRegister = getCacheControlRegister();
139 unsigned int iTE;
63 // set the bit IB to 1
140 unsigned int iDE;
64 cacheControlRegister = (cacheControlRegister | 0x10000);
141 unsigned int dTE;
65 setCacheControlRegister(cacheControlRegister);
142 unsigned int dDE;
66 #endif
143
144 cacheControlRegister = CCR_getValue();
145 iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
146 iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
147 dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
148 dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
149
150 *instructionErrorCounter = iTE + iDE;
151 *dataErrorCounter = dTE + dDE;
152
153 // reset counters
154 cacheControlRegister = cacheControlRegister
155 & COUNTER_FIELD_ITE
156 & COUNTER_FIELD_IDE
157 & COUNTER_FIELD_DTE
158 & COUNTER_FIELD_DDE;
159
160 CCR_setValue(cacheControlRegister);
161 }
162
163 //*******************************************
164 // ASR16 Register protection control register
165
166 static unsigned int ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
167 {
168 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
169 * register file error counter
170 *
171 * @return void
172 *
173 * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
174 * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
175 *
176 */
177
178 unsigned int asr16;
179
180 asr16 = *asr16Ptr;
181 *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
182 *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
183
184 // reset the counter to 0
185 asr16 = asr16Ptr
186 & COUNTER_MASK_FPRF
187 & COUNTER_FIELD_IURF;
188
189 *asr16Ptr = asr16;
67 }
190 }
68
191
69 #endif /* GSCMEMORY_HPP_ */
192 #endif /* GSCMEMORY_HPP_ */
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@@ -64,19 +64,38
64
64
65 void initCache()
65 void initCache()
66 {
66 {
67 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
68 // These should only be read and written using 32-bit LDA/STA instructions.
69 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
70 // The table below shows the register addresses:
71 // 0x00 Cache control register
72 // 0x04 Reserved
73 // 0x08 Instruction cache configuration register
74 // 0x0C Data cache configuration register
75
76 // Cache Control Register Leon3 / Leon3FT
77 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
78 // RFT PS TB DS FD FI FT ST IB
79 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
80 // IP DP ITE IDE DTE DDE DF IF DCS ICS
81
67 unsigned int cacheControlRegister;
82 unsigned int cacheControlRegister;
68
83
69 cacheControlRegister = getCacheControlRegister();
84 cacheControlRegister = CCR_getValue();
70 PRINTF1("(0) cacheControlRegister = %x\n", cacheControlRegister)
85 PRINTF1("(0) cacheControlRegister = %x\n", cacheControlRegister);
71
86
72 resetCacheControlRegister();
87 CCR_resetCacheControlRegister();
73
88
74 enableInstructionCache();
89 CCR_enableInstructionCache(); // ICS bits
75 enableDataCache();
90 CCR_enableDataCache(); // DCS bits
76 enableInstructionBurstFetch();
91 CCR_enableInstructionBurstFetch(); // IB bit
77
92
78 cacheControlRegister = getCacheControlRegister();
93 cacheControlRegister = CCR_getValue();
79 PRINTF1("(1) cacheControlRegister = %x\n", cacheControlRegister)
94 PRINTF1("(1) cacheControlRegister = %x\n", cacheControlRegister);
95
96 CCR_faultTolerantScheme();
97
98 // FT activation
80 }
99 }
81
100
82 rtems_task Init( rtems_task_argument ignored )
101 rtems_task Init( rtems_task_argument ignored )
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@@ -117,6 +117,9 void watchdog_reload(void)
117 {
117 {
118 /** This function reloads the watchdog timer counter with the timer reload value.
118 /** This function reloads the watchdog timer counter with the timer reload value.
119 *
119 *
120 * @param void
121 *
122 * @return void
120 *
123 *
121 */
124 */
122
125
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