##// END OF EJS Templates
major change in fsw_processing.h to save cpu load
paul -
r325:b06a3a324978 R3_plus draft
parent child
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@@ -1,380 +1,371
1 #ifndef FSW_PROCESSING_H_INCLUDED
1 #ifndef FSW_PROCESSING_H_INCLUDED
2 #define FSW_PROCESSING_H_INCLUDED
2 #define FSW_PROCESSING_H_INCLUDED
3
3
4 #include <rtems.h>
4 #include <rtems.h>
5 #include <grspw.h>
5 #include <grspw.h>
6 #include <math.h>
6 #include <math.h>
7 #include <stdlib.h> // abs() is in the stdlib
7 #include <stdlib.h> // abs() is in the stdlib
8 #include <stdio.h>
8 #include <stdio.h>
9 #include <math.h>
9 #include <math.h>
10 #include <grlib_regs.h>
10 #include <grlib_regs.h>
11
11
12 #include "fsw_params.h"
12 #include "fsw_params.h"
13
13
14 #define SBM_COEFF_PER_NORM_COEFF 2
14 #define SBM_COEFF_PER_NORM_COEFF 2
15 #define MAX_SRC_DATA 780 // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
15 #define MAX_SRC_DATA 780 // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
16 #define MAX_SRC_DATA_WITH_SPARE 143 // 13 bins * 11 Bytes
16 #define MAX_SRC_DATA_WITH_SPARE 143 // 13 bins * 11 Bytes
17
17
18 #define NODE_0 0
18 #define NODE_0 0
19 #define NODE_1 1
19 #define NODE_1 1
20 #define NODE_2 2
20 #define NODE_2 2
21 #define NODE_3 3
21 #define NODE_3 3
22 #define NODE_4 4
22 #define NODE_4 4
23 #define NODE_5 5
23 #define NODE_5 5
24 #define NODE_6 6
24 #define NODE_6 6
25 #define NODE_7 7
25 #define NODE_7 7
26
26
27 typedef struct ring_node_asm
27 typedef struct ring_node_asm
28 {
28 {
29 struct ring_node_asm *next;
29 struct ring_node_asm *next;
30 float matrix[ TOTAL_SIZE_SM ];
30 float matrix[ TOTAL_SIZE_SM ];
31 unsigned int status;
31 unsigned int status;
32 } ring_node_asm;
32 } ring_node_asm;
33
33
34 typedef struct
34 typedef struct
35 {
35 {
36 unsigned char targetLogicalAddress;
36 unsigned char targetLogicalAddress;
37 unsigned char protocolIdentifier;
37 unsigned char protocolIdentifier;
38 unsigned char reserved;
38 unsigned char reserved;
39 unsigned char userApplication;
39 unsigned char userApplication;
40 unsigned char packetID[BYTES_PER_PACKETID];
40 unsigned char packetID[BYTES_PER_PACKETID];
41 unsigned char packetSequenceControl[BYTES_PER_SEQ_CTRL];
41 unsigned char packetSequenceControl[BYTES_PER_SEQ_CTRL];
42 unsigned char packetLength[BYTES_PER_PKT_LEN];
42 unsigned char packetLength[BYTES_PER_PKT_LEN];
43 // DATA FIELD HEADER
43 // DATA FIELD HEADER
44 unsigned char spare1_pusVersion_spare2;
44 unsigned char spare1_pusVersion_spare2;
45 unsigned char serviceType;
45 unsigned char serviceType;
46 unsigned char serviceSubType;
46 unsigned char serviceSubType;
47 unsigned char destinationID;
47 unsigned char destinationID;
48 unsigned char time[BYTES_PER_TIME];
48 unsigned char time[BYTES_PER_TIME];
49 // AUXILIARY HEADER
49 // AUXILIARY HEADER
50 unsigned char sid;
50 unsigned char sid;
51 unsigned char pa_bia_status_info;
51 unsigned char pa_bia_status_info;
52 unsigned char sy_lfr_common_parameters_spare;
52 unsigned char sy_lfr_common_parameters_spare;
53 unsigned char sy_lfr_common_parameters;
53 unsigned char sy_lfr_common_parameters;
54 unsigned char acquisitionTime[BYTES_PER_TIME];
54 unsigned char acquisitionTime[BYTES_PER_TIME];
55 unsigned char pa_lfr_bp_blk_nr[BYTES_PER_BLKNR];
55 unsigned char pa_lfr_bp_blk_nr[BYTES_PER_BLKNR];
56 // SOURCE DATA
56 // SOURCE DATA
57 unsigned char data[ MAX_SRC_DATA ]; // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
57 unsigned char data[ MAX_SRC_DATA ]; // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
58 } bp_packet;
58 } bp_packet;
59
59
60 typedef struct
60 typedef struct
61 {
61 {
62 unsigned char targetLogicalAddress;
62 unsigned char targetLogicalAddress;
63 unsigned char protocolIdentifier;
63 unsigned char protocolIdentifier;
64 unsigned char reserved;
64 unsigned char reserved;
65 unsigned char userApplication;
65 unsigned char userApplication;
66 unsigned char packetID[BYTES_PER_PACKETID];
66 unsigned char packetID[BYTES_PER_PACKETID];
67 unsigned char packetSequenceControl[BYTES_PER_SEQ_CTRL];
67 unsigned char packetSequenceControl[BYTES_PER_SEQ_CTRL];
68 unsigned char packetLength[BYTES_PER_PKT_LEN];
68 unsigned char packetLength[BYTES_PER_PKT_LEN];
69 // DATA FIELD HEADER
69 // DATA FIELD HEADER
70 unsigned char spare1_pusVersion_spare2;
70 unsigned char spare1_pusVersion_spare2;
71 unsigned char serviceType;
71 unsigned char serviceType;
72 unsigned char serviceSubType;
72 unsigned char serviceSubType;
73 unsigned char destinationID;
73 unsigned char destinationID;
74 unsigned char time[BYTES_PER_TIME];
74 unsigned char time[BYTES_PER_TIME];
75 // AUXILIARY HEADER
75 // AUXILIARY HEADER
76 unsigned char sid;
76 unsigned char sid;
77 unsigned char pa_bia_status_info;
77 unsigned char pa_bia_status_info;
78 unsigned char sy_lfr_common_parameters_spare;
78 unsigned char sy_lfr_common_parameters_spare;
79 unsigned char sy_lfr_common_parameters;
79 unsigned char sy_lfr_common_parameters;
80 unsigned char acquisitionTime[BYTES_PER_TIME];
80 unsigned char acquisitionTime[BYTES_PER_TIME];
81 unsigned char source_data_spare;
81 unsigned char source_data_spare;
82 unsigned char pa_lfr_bp_blk_nr[BYTES_PER_BLKNR];
82 unsigned char pa_lfr_bp_blk_nr[BYTES_PER_BLKNR];
83 // SOURCE DATA
83 // SOURCE DATA
84 unsigned char data[ MAX_SRC_DATA_WITH_SPARE ]; // 13 bins * 11 Bytes
84 unsigned char data[ MAX_SRC_DATA_WITH_SPARE ]; // 13 bins * 11 Bytes
85 } bp_packet_with_spare; // only for TM_LFR_SCIENCE_NORMAL_BP1_F0 and F1
85 } bp_packet_with_spare; // only for TM_LFR_SCIENCE_NORMAL_BP1_F0 and F1
86
86
87 typedef struct asm_msg
87 typedef struct asm_msg
88 {
88 {
89 ring_node_asm *norm;
89 ring_node_asm *norm;
90 ring_node_asm *burst_sbm;
90 ring_node_asm *burst_sbm;
91 rtems_event_set event;
91 rtems_event_set event;
92 unsigned int coarseTimeNORM;
92 unsigned int coarseTimeNORM;
93 unsigned int fineTimeNORM;
93 unsigned int fineTimeNORM;
94 unsigned int coarseTimeSBM;
94 unsigned int coarseTimeSBM;
95 unsigned int fineTimeSBM;
95 unsigned int fineTimeSBM;
96 unsigned int numberOfSMInASMNORM;
96 unsigned int numberOfSMInASMNORM;
97 unsigned int numberOfSMInASMSBM;
97 unsigned int numberOfSMInASMSBM;
98 } asm_msg;
98 } asm_msg;
99
99
100 extern unsigned char thisIsAnASMRestart;
100 extern unsigned char thisIsAnASMRestart;
101
101
102 extern volatile int sm_f0[ ];
102 extern volatile int sm_f0[ ];
103 extern volatile int sm_f1[ ];
103 extern volatile int sm_f1[ ];
104 extern volatile int sm_f2[ ];
104 extern volatile int sm_f2[ ];
105 extern unsigned int acquisitionDurations[];
105 extern unsigned int acquisitionDurations[];
106
106
107 // parameters
107 // parameters
108 extern struct param_local_str param_local;
108 extern struct param_local_str param_local;
109 extern Packet_TM_LFR_PARAMETER_DUMP_t parameter_dump_packet;
109 extern Packet_TM_LFR_PARAMETER_DUMP_t parameter_dump_packet;
110
110
111 // registers
111 // registers
112 extern time_management_regs_t *time_management_regs;
112 extern time_management_regs_t *time_management_regs;
113 extern volatile spectral_matrix_regs_t *spectral_matrix_regs;
113 extern volatile spectral_matrix_regs_t *spectral_matrix_regs;
114
114
115 extern rtems_name misc_name[];
115 extern rtems_name misc_name[];
116 extern rtems_id Task_id[]; /* array of task ids */
116 extern rtems_id Task_id[]; /* array of task ids */
117
117
118 ring_node * getRingNodeForAveraging( unsigned char frequencyChannel);
118 ring_node * getRingNodeForAveraging( unsigned char frequencyChannel);
119 // ISR
119 // ISR
120 rtems_isr spectral_matrices_isr( rtems_vector_number vector );
120 rtems_isr spectral_matrices_isr( rtems_vector_number vector );
121
121
122 //******************
122 //******************
123 // Spectral Matrices
123 // Spectral Matrices
124 void reset_nb_sm( void );
124 void reset_nb_sm( void );
125 // SM
125 // SM
126 void SM_init_rings( void );
126 void SM_init_rings( void );
127 void SM_reset_current_ring_nodes( void );
127 void SM_reset_current_ring_nodes( void );
128 // ASM
128 // ASM
129 void ASM_generic_init_ring(ring_node_asm *ring, unsigned char nbNodes );
129 void ASM_generic_init_ring(ring_node_asm *ring, unsigned char nbNodes );
130
130
131 //*****************
131 //*****************
132 // Basic Parameters
132 // Basic Parameters
133
133
134 void BP_reset_current_ring_nodes( void );
134 void BP_reset_current_ring_nodes( void );
135 void BP_init_header(bp_packet *packet,
135 void BP_init_header(bp_packet *packet,
136 unsigned int apid, unsigned char sid,
136 unsigned int apid, unsigned char sid,
137 unsigned int packetLength , unsigned char blkNr);
137 unsigned int packetLength , unsigned char blkNr);
138 void BP_init_header_with_spare(bp_packet_with_spare *packet,
138 void BP_init_header_with_spare(bp_packet_with_spare *packet,
139 unsigned int apid, unsigned char sid,
139 unsigned int apid, unsigned char sid,
140 unsigned int packetLength, unsigned char blkNr );
140 unsigned int packetLength, unsigned char blkNr );
141 void BP_send( char *data,
141 void BP_send( char *data,
142 rtems_id queue_id,
142 rtems_id queue_id,
143 unsigned int nbBytesToSend , unsigned int sid );
143 unsigned int nbBytesToSend , unsigned int sid );
144 void BP_send_s1_s2(char *data,
144 void BP_send_s1_s2(char *data,
145 rtems_id queue_id,
145 rtems_id queue_id,
146 unsigned int nbBytesToSend, unsigned int sid );
146 unsigned int nbBytesToSend, unsigned int sid );
147
147
148 //******************
148 //******************
149 // general functions
149 // general functions
150 void reset_sm_status( void );
150 void reset_sm_status( void );
151 void reset_spectral_matrix_regs( void );
151 void reset_spectral_matrix_regs( void );
152 void set_time(unsigned char *time, unsigned char *timeInBuffer );
152 void set_time(unsigned char *time, unsigned char *timeInBuffer );
153 unsigned long long int get_acquisition_time( unsigned char *timePtr );
153 unsigned long long int get_acquisition_time( unsigned char *timePtr );
154 unsigned char getSID( rtems_event_set event );
154 unsigned char getSID( rtems_event_set event );
155
155
156 extern rtems_status_code get_message_queue_id_prc1( rtems_id *queue_id );
156 extern rtems_status_code get_message_queue_id_prc1( rtems_id *queue_id );
157 extern rtems_status_code get_message_queue_id_prc2( rtems_id *queue_id );
157 extern rtems_status_code get_message_queue_id_prc2( rtems_id *queue_id );
158
158
159 //***************************************
159 //***************************************
160 // DEFINITIONS OF STATIC INLINE FUNCTIONS
160 // DEFINITIONS OF STATIC INLINE FUNCTIONS
161 static inline void SM_average(float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
161 static inline void SM_average(float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
162 ring_node *ring_node_tab[],
162 ring_node *ring_node_tab[],
163 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
163 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
164 asm_msg *msgForMATR , unsigned char channel);
164 asm_msg *msgForMATR , unsigned char channel);
165
165
166 void ASM_patch( float *inputASM, float *outputASM );
166 void ASM_patch( float *inputASM, float *outputASM );
167
167
168 void extractReImVectors(float *inputASM, float *outputASM, unsigned int asmComponent );
168 void extractReImVectors(float *inputASM, float *outputASM, unsigned int asmComponent );
169
169
170 static inline void ASM_reorganize_and_divide(float *averaged_spec_mat, float *averaged_spec_mat_reorganized,
170 static inline void ASM_reorganize_and_divide(float *averaged_spec_mat, float *averaged_spec_mat_reorganized,
171 float divider );
171 float divider );
172
172
173 static inline void ASM_compress_reorganize_and_divide(float *averaged_spec_mat, float *compressed_spec_mat,
173 static inline void ASM_compress_reorganize_and_divide(float *averaged_spec_mat, float *compressed_spec_mat,
174 float divider,
174 float divider,
175 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage , unsigned char ASMIndexStart);
175 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage , unsigned char ASMIndexStart);
176
176
177 static inline void ASM_convert(volatile float *input_matrix, char *output_matrix);
177 static inline void ASM_convert(volatile float *input_matrix, char *output_matrix);
178
178
179 unsigned char acquisitionTimeIsValid(unsigned int coarseTime, unsigned int fineTime, unsigned char channel);
179 unsigned char acquisitionTimeIsValid(unsigned int coarseTime, unsigned int fineTime, unsigned char channel);
180
180
181 void SM_average( float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
181 void SM_average( float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
182 ring_node *ring_node_tab[],
182 ring_node *ring_node_tab[],
183 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
183 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
184 asm_msg *msgForMATR, unsigned char channel )
184 asm_msg *msgForMATR, unsigned char channel )
185 {
185 {
186 float sum;
186 float sum;
187 unsigned int i;
187 unsigned int i;
188 unsigned int k;
188 unsigned int k;
189 unsigned char incomingSMIsValid[NB_SM_BEFORE_AVF0_F1];
189 unsigned char incomingSMIsValid[NB_SM_BEFORE_AVF0_F1];
190 unsigned int numberOfValidSM;
190 unsigned int numberOfValidSM;
191 unsigned char isValid;
191 unsigned char isValid;
192
192
193 //**************
193 //**************
194 // PAS FILTERING
194 // PAS FILTERING
195 // check acquisitionTime of the incoming data
195 // check acquisitionTime of the incoming data
196 numberOfValidSM = 0;
196 numberOfValidSM = 0;
197 for (k=0; k<NB_SM_BEFORE_AVF0_F1; k++)
197 for (k=0; k<NB_SM_BEFORE_AVF0_F1; k++)
198 {
198 {
199 isValid = acquisitionTimeIsValid( ring_node_tab[k]->coarseTime, ring_node_tab[k]->fineTime, channel );
199 isValid = acquisitionTimeIsValid( ring_node_tab[k]->coarseTime, ring_node_tab[k]->fineTime, channel );
200 incomingSMIsValid[k] = isValid;
200 incomingSMIsValid[k] = isValid;
201 numberOfValidSM = numberOfValidSM + isValid;
201 numberOfValidSM = numberOfValidSM + isValid;
202 }
202 }
203
203
204 //************************
204 //************************
205 // AVERAGE SPECTRAL MATRIX
205 // AVERAGE SPECTRAL MATRIX
206 for(i=0; i<TOTAL_SIZE_SM; i++)
206 for(i=0; i<TOTAL_SIZE_SM; i++)
207 {
207 {
208 // sum = ( (int *) (ring_node_tab[0]->buffer_address) ) [ i ]
208 sum = INIT_FLOAT;
209 // + ( (int *) (ring_node_tab[1]->buffer_address) ) [ i ]
209 for ( k = 0; k < NB_SM_BEFORE_AVF0_F1; k++ )
210 // + ( (int *) (ring_node_tab[2]->buffer_address) ) [ i ]
210 {
211 // + ( (int *) (ring_node_tab[3]->buffer_address) ) [ i ]
211 if (incomingSMIsValid[k] == 1)
212 // + ( (int *) (ring_node_tab[4]->buffer_address) ) [ i ]
212 {
213 // + ( (int *) (ring_node_tab[5]->buffer_address) ) [ i ]
213 sum = sum + ( (int *) (ring_node_tab[0]->buffer_address) ) [ i ] ;
214 // + ( (int *) (ring_node_tab[6]->buffer_address) ) [ i ]
214 }
215 // + ( (int *) (ring_node_tab[7]->buffer_address) ) [ i ];
215 }
216
217 sum = ( incomingSMIsValid[BYTE_0] * ((int *)(ring_node_tab[NODE_0]->buffer_address) )[ i ] )
218 + ( incomingSMIsValid[BYTE_1] * ((int *)(ring_node_tab[NODE_1]->buffer_address) )[ i ] )
219 + ( incomingSMIsValid[BYTE_2] * ((int *)(ring_node_tab[NODE_2]->buffer_address) )[ i ] )
220 + ( incomingSMIsValid[BYTE_3] * ((int *)(ring_node_tab[NODE_3]->buffer_address) )[ i ] )
221 + ( incomingSMIsValid[BYTE_4] * ((int *)(ring_node_tab[NODE_4]->buffer_address) )[ i ] )
222 + ( incomingSMIsValid[BYTE_5] * ((int *)(ring_node_tab[NODE_5]->buffer_address) )[ i ] )
223 + ( incomingSMIsValid[BYTE_6] * ((int *)(ring_node_tab[NODE_6]->buffer_address) )[ i ] )
224 + ( incomingSMIsValid[BYTE_7] * ((int *)(ring_node_tab[NODE_7]->buffer_address) )[ i ] );
225
216
226 if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) )
217 if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) )
227 {
218 {
228 averaged_spec_mat_NORM[ i ] = sum;
219 averaged_spec_mat_NORM[ i ] = sum;
229 averaged_spec_mat_SBM[ i ] = sum;
220 averaged_spec_mat_SBM[ i ] = sum;
230 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
221 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
231 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
222 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
232 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
223 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
233 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
224 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
234 }
225 }
235 else if ( (nbAverageNORM != 0) && (nbAverageSBM != 0) )
226 else if ( (nbAverageNORM != 0) && (nbAverageSBM != 0) )
236 {
227 {
237 averaged_spec_mat_NORM[ i ] = ( averaged_spec_mat_NORM[ i ] + sum );
228 averaged_spec_mat_NORM[ i ] = ( averaged_spec_mat_NORM[ i ] + sum );
238 averaged_spec_mat_SBM[ i ] = ( averaged_spec_mat_SBM[ i ] + sum );
229 averaged_spec_mat_SBM[ i ] = ( averaged_spec_mat_SBM[ i ] + sum );
239 }
230 }
240 else if ( (nbAverageNORM != 0) && (nbAverageSBM == 0) )
231 else if ( (nbAverageNORM != 0) && (nbAverageSBM == 0) )
241 {
232 {
242 averaged_spec_mat_NORM[ i ] = ( averaged_spec_mat_NORM[ i ] + sum );
233 averaged_spec_mat_NORM[ i ] = ( averaged_spec_mat_NORM[ i ] + sum );
243 averaged_spec_mat_SBM[ i ] = sum;
234 averaged_spec_mat_SBM[ i ] = sum;
244 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
235 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
245 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
236 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
246 }
237 }
247 else
238 else
248 {
239 {
249 averaged_spec_mat_NORM[ i ] = sum;
240 averaged_spec_mat_NORM[ i ] = sum;
250 averaged_spec_mat_SBM[ i ] = ( averaged_spec_mat_SBM[ i ] + sum );
241 averaged_spec_mat_SBM[ i ] = ( averaged_spec_mat_SBM[ i ] + sum );
251 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
242 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
252 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
243 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
253 // PRINTF2("ERR *** in SM_average *** unexpected parameters %d %d\n", nbAverageNORM, nbAverageSBM)
244 // PRINTF2("ERR *** in SM_average *** unexpected parameters %d %d\n", nbAverageNORM, nbAverageSBM)
254 }
245 }
255 }
246 }
256
247
257 //*******************
248 //*******************
258 // UPDATE SM COUNTERS
249 // UPDATE SM COUNTERS
259 if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) )
250 if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) )
260 {
251 {
261 msgForMATR->numberOfSMInASMNORM = numberOfValidSM;
252 msgForMATR->numberOfSMInASMNORM = numberOfValidSM;
262 msgForMATR->numberOfSMInASMSBM = numberOfValidSM;
253 msgForMATR->numberOfSMInASMSBM = numberOfValidSM;
263 }
254 }
264 else if ( (nbAverageNORM != 0) && (nbAverageSBM != 0) )
255 else if ( (nbAverageNORM != 0) && (nbAverageSBM != 0) )
265 {
256 {
266 msgForMATR->numberOfSMInASMNORM = msgForMATR->numberOfSMInASMNORM + numberOfValidSM;
257 msgForMATR->numberOfSMInASMNORM = msgForMATR->numberOfSMInASMNORM + numberOfValidSM;
267 msgForMATR->numberOfSMInASMSBM = msgForMATR->numberOfSMInASMSBM + numberOfValidSM;
258 msgForMATR->numberOfSMInASMSBM = msgForMATR->numberOfSMInASMSBM + numberOfValidSM;
268 }
259 }
269 else if ( (nbAverageNORM != 0) && (nbAverageSBM == 0) )
260 else if ( (nbAverageNORM != 0) && (nbAverageSBM == 0) )
270 {
261 {
271 msgForMATR->numberOfSMInASMNORM = msgForMATR->numberOfSMInASMNORM + numberOfValidSM;
262 msgForMATR->numberOfSMInASMNORM = msgForMATR->numberOfSMInASMNORM + numberOfValidSM;
272 msgForMATR->numberOfSMInASMSBM = numberOfValidSM;
263 msgForMATR->numberOfSMInASMSBM = numberOfValidSM;
273 }
264 }
274 else
265 else
275 {
266 {
276 msgForMATR->numberOfSMInASMNORM = numberOfValidSM;
267 msgForMATR->numberOfSMInASMNORM = numberOfValidSM;
277 msgForMATR->numberOfSMInASMSBM = msgForMATR->numberOfSMInASMSBM + numberOfValidSM;
268 msgForMATR->numberOfSMInASMSBM = msgForMATR->numberOfSMInASMSBM + numberOfValidSM;
278 }
269 }
279 }
270 }
280
271
281 void ASM_reorganize_and_divide( float *averaged_spec_mat, float *averaged_spec_mat_reorganized, float divider )
272 void ASM_reorganize_and_divide( float *averaged_spec_mat, float *averaged_spec_mat_reorganized, float divider )
282 {
273 {
283 int frequencyBin;
274 int frequencyBin;
284 int asmComponent;
275 int asmComponent;
285 unsigned int offsetASM;
276 unsigned int offsetASM;
286 unsigned int offsetASMReorganized;
277 unsigned int offsetASMReorganized;
287
278
288 // BUILD DATA
279 // BUILD DATA
289 for (asmComponent = 0; asmComponent < NB_VALUES_PER_SM; asmComponent++)
280 for (asmComponent = 0; asmComponent < NB_VALUES_PER_SM; asmComponent++)
290 {
281 {
291 for( frequencyBin = 0; frequencyBin < NB_BINS_PER_SM; frequencyBin++ )
282 for( frequencyBin = 0; frequencyBin < NB_BINS_PER_SM; frequencyBin++ )
292 {
283 {
293 offsetASMReorganized =
284 offsetASMReorganized =
294 (frequencyBin * NB_VALUES_PER_SM)
285 (frequencyBin * NB_VALUES_PER_SM)
295 + asmComponent;
286 + asmComponent;
296 offsetASM =
287 offsetASM =
297 (asmComponent * NB_BINS_PER_SM)
288 (asmComponent * NB_BINS_PER_SM)
298 + frequencyBin;
289 + frequencyBin;
299 if ( divider != INIT_FLOAT )
290 if ( divider != INIT_FLOAT )
300 {
291 {
301 averaged_spec_mat_reorganized[offsetASMReorganized ] = averaged_spec_mat[ offsetASM ] / divider;
292 averaged_spec_mat_reorganized[offsetASMReorganized ] = averaged_spec_mat[ offsetASM ] / divider;
302 }
293 }
303 else
294 else
304 {
295 {
305 averaged_spec_mat_reorganized[offsetASMReorganized ] = INIT_FLOAT;
296 averaged_spec_mat_reorganized[offsetASMReorganized ] = INIT_FLOAT;
306 }
297 }
307 }
298 }
308 }
299 }
309 }
300 }
310
301
311 void ASM_compress_reorganize_and_divide(float *averaged_spec_mat, float *compressed_spec_mat , float divider,
302 void ASM_compress_reorganize_and_divide(float *averaged_spec_mat, float *compressed_spec_mat , float divider,
312 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage, unsigned char ASMIndexStart )
303 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage, unsigned char ASMIndexStart )
313 {
304 {
314 int frequencyBin;
305 int frequencyBin;
315 int asmComponent;
306 int asmComponent;
316 int offsetASM;
307 int offsetASM;
317 int offsetCompressed;
308 int offsetCompressed;
318 int k;
309 int k;
319
310
320 // BUILD DATA
311 // BUILD DATA
321 for (asmComponent = 0; asmComponent < NB_VALUES_PER_SM; asmComponent++)
312 for (asmComponent = 0; asmComponent < NB_VALUES_PER_SM; asmComponent++)
322 {
313 {
323 for( frequencyBin = 0; frequencyBin < nbBinsCompressedMatrix; frequencyBin++ )
314 for( frequencyBin = 0; frequencyBin < nbBinsCompressedMatrix; frequencyBin++ )
324 {
315 {
325 offsetCompressed = // NO TIME OFFSET
316 offsetCompressed = // NO TIME OFFSET
326 (frequencyBin * NB_VALUES_PER_SM)
317 (frequencyBin * NB_VALUES_PER_SM)
327 + asmComponent;
318 + asmComponent;
328 offsetASM = // NO TIME OFFSET
319 offsetASM = // NO TIME OFFSET
329 (asmComponent * NB_BINS_PER_SM)
320 (asmComponent * NB_BINS_PER_SM)
330 + ASMIndexStart
321 + ASMIndexStart
331 + (frequencyBin * nbBinsToAverage);
322 + (frequencyBin * nbBinsToAverage);
332 compressed_spec_mat[ offsetCompressed ] = 0;
323 compressed_spec_mat[ offsetCompressed ] = 0;
333 for ( k = 0; k < nbBinsToAverage; k++ )
324 for ( k = 0; k < nbBinsToAverage; k++ )
334 {
325 {
335 compressed_spec_mat[offsetCompressed ] =
326 compressed_spec_mat[offsetCompressed ] =
336 ( compressed_spec_mat[ offsetCompressed ]
327 ( compressed_spec_mat[ offsetCompressed ]
337 + averaged_spec_mat[ offsetASM + k ] );
328 + averaged_spec_mat[ offsetASM + k ] );
338 }
329 }
339 compressed_spec_mat[ offsetCompressed ] =
330 compressed_spec_mat[ offsetCompressed ] =
340 compressed_spec_mat[ offsetCompressed ] / (divider * nbBinsToAverage);
331 compressed_spec_mat[ offsetCompressed ] / (divider * nbBinsToAverage);
341 }
332 }
342 }
333 }
343 }
334 }
344
335
345 void ASM_convert( volatile float *input_matrix, char *output_matrix)
336 void ASM_convert( volatile float *input_matrix, char *output_matrix)
346 {
337 {
347 unsigned int frequencyBin;
338 unsigned int frequencyBin;
348 unsigned int asmComponent;
339 unsigned int asmComponent;
349 char * pt_char_input;
340 char * pt_char_input;
350 char * pt_char_output;
341 char * pt_char_output;
351 unsigned int offsetInput;
342 unsigned int offsetInput;
352 unsigned int offsetOutput;
343 unsigned int offsetOutput;
353
344
354 pt_char_input = (char*) &input_matrix;
345 pt_char_input = (char*) &input_matrix;
355 pt_char_output = (char*) &output_matrix;
346 pt_char_output = (char*) &output_matrix;
356
347
357 // convert all other data
348 // convert all other data
358 for( frequencyBin=0; frequencyBin<NB_BINS_PER_SM; frequencyBin++)
349 for( frequencyBin=0; frequencyBin<NB_BINS_PER_SM; frequencyBin++)
359 {
350 {
360 for ( asmComponent=0; asmComponent<NB_VALUES_PER_SM; asmComponent++)
351 for ( asmComponent=0; asmComponent<NB_VALUES_PER_SM; asmComponent++)
361 {
352 {
362 offsetInput = (frequencyBin*NB_VALUES_PER_SM) + asmComponent ;
353 offsetInput = (frequencyBin*NB_VALUES_PER_SM) + asmComponent ;
363 offsetOutput = SM_BYTES_PER_VAL * ( (frequencyBin*NB_VALUES_PER_SM) + asmComponent ) ;
354 offsetOutput = SM_BYTES_PER_VAL * ( (frequencyBin*NB_VALUES_PER_SM) + asmComponent ) ;
364 pt_char_input = (char*) &input_matrix [ offsetInput ];
355 pt_char_input = (char*) &input_matrix [ offsetInput ];
365 pt_char_output = (char*) &output_matrix[ offsetOutput ];
356 pt_char_output = (char*) &output_matrix[ offsetOutput ];
366 pt_char_output[0] = pt_char_input[0]; // bits 31 downto 24 of the float
357 pt_char_output[0] = pt_char_input[0]; // bits 31 downto 24 of the float
367 pt_char_output[1] = pt_char_input[1]; // bits 23 downto 16 of the float
358 pt_char_output[1] = pt_char_input[1]; // bits 23 downto 16 of the float
368 }
359 }
369 }
360 }
370 }
361 }
371
362
372 void ASM_compress_reorganize_and_divide_mask(float *averaged_spec_mat, float *compressed_spec_mat,
363 void ASM_compress_reorganize_and_divide_mask(float *averaged_spec_mat, float *compressed_spec_mat,
373 float divider,
364 float divider,
374 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage , unsigned char ASMIndexStart, unsigned char channel);
365 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage , unsigned char ASMIndexStart, unsigned char channel);
375
366
376 int getFBinMask(int k, unsigned char channel);
367 int getFBinMask(int k, unsigned char channel);
377
368
378 void init_kcoeff_sbm_from_kcoeff_norm( float *input_kcoeff, float *output_kcoeff, unsigned char nb_bins_norm);
369 void init_kcoeff_sbm_from_kcoeff_norm( float *input_kcoeff, float *output_kcoeff, unsigned char nb_bins_norm);
379
370
380 #endif // FSW_PROCESSING_H_INCLUDED
371 #endif // FSW_PROCESSING_H_INCLUDED
@@ -1,108 +1,107
1 cmake_minimum_required (VERSION 2.6)
1 cmake_minimum_required (VERSION 2.6)
2 project (fsw)
2 project (fsw)
3
3
4 include(sparc-rtems)
4 include(sparc-rtems)
5 include(cppcheck)
5 include(cppcheck)
6
6
7 include_directories("../header"
7 include_directories("../header"
8 "../header/lfr_common_headers"
8 "../header/lfr_common_headers"
9 "../header/processing"
9 "../header/processing"
10 "../LFR_basic-parameters"
10 "../LFR_basic-parameters"
11 "../src")
11 "../src")
12
12
13 set(SOURCES wf_handler.c
13 set(SOURCES wf_handler.c
14 tc_handler.c
14 tc_handler.c
15 fsw_misc.c
15 fsw_misc.c
16 fsw_init.c
16 fsw_init.c
17 fsw_globals.c
17 fsw_globals.c
18 fsw_spacewire.c
18 fsw_spacewire.c
19 tc_load_dump_parameters.c
19 tc_load_dump_parameters.c
20 tm_lfr_tc_exe.c
20 tm_lfr_tc_exe.c
21 tc_acceptance.c
21 tc_acceptance.c
22 processing/fsw_processing.c
22 processing/fsw_processing.c
23 processing/avf0_prc0.c
23 processing/avf0_prc0.c
24 processing/avf1_prc1.c
24 processing/avf1_prc1.c
25 processing/avf2_prc2.c
25 processing/avf2_prc2.c
26 lfr_cpu_usage_report.c
26 lfr_cpu_usage_report.c
27 ${LFR_BP_SRC}
27 ${LFR_BP_SRC}
28 ../header/wf_handler.h
28 ../header/wf_handler.h
29 ../header/tc_handler.h
29 ../header/tc_handler.h
30 ../header/grlib_regs.h
30 ../header/grlib_regs.h
31 ../header/fsw_misc.h
31 ../header/fsw_misc.h
32 ../header/fsw_init.h
32 ../header/fsw_init.h
33 ../header/fsw_spacewire.h
33 ../header/fsw_spacewire.h
34 ../header/tc_load_dump_parameters.h
34 ../header/tc_load_dump_parameters.h
35 ../header/tm_lfr_tc_exe.h
35 ../header/tm_lfr_tc_exe.h
36 ../header/tc_acceptance.h
36 ../header/tc_acceptance.h
37 ../header/processing/fsw_processing.h
37 ../header/processing/fsw_processing.h
38 ../header/processing/avf0_prc0.h
38 ../header/processing/avf0_prc0.h
39 ../header/processing/avf1_prc1.h
39 ../header/processing/avf1_prc1.h
40 ../header/processing/avf2_prc2.h
40 ../header/processing/avf2_prc2.h
41 ../header/fsw_params_wf_handler.h
41 ../header/fsw_params_wf_handler.h
42 ../header/lfr_cpu_usage_report.h
42 ../header/lfr_cpu_usage_report.h
43 ../header/lfr_common_headers/ccsds_types.h
43 ../header/lfr_common_headers/ccsds_types.h
44 ../header/lfr_common_headers/fsw_params.h
44 ../header/lfr_common_headers/fsw_params.h
45 ../header/lfr_common_headers/fsw_params_nb_bytes.h
45 ../header/lfr_common_headers/fsw_params_nb_bytes.h
46 ../header/lfr_common_headers/fsw_params_processing.h
46 ../header/lfr_common_headers/fsw_params_processing.h
47 ../header/lfr_common_headers/tm_byte_positions.h
47 ../header/lfr_common_headers/tm_byte_positions.h
48 ../LFR_basic-parameters/basic_parameters.h
48 ../LFR_basic-parameters/basic_parameters.h
49 ../LFR_basic-parameters/basic_parameters_params.h
49 ../LFR_basic-parameters/basic_parameters_params.h
50 ../header/GscMemoryLPP.hpp
50 ../header/GscMemoryLPP.hpp
51 )
51 )
52
52
53
53
54 option(FSW_verbose "Enable verbose LFR" ON)
54 option(FSW_verbose "Enable verbose LFR" ON)
55 option(FSW_boot_messages "Enable LFR boot messages" ON)
55 option(FSW_boot_messages "Enable LFR boot messages" ON)
56 option(FSW_debug_messages "Enable LFR debug messages" ON)
56 option(FSW_debug_messages "Enable LFR debug messages" ON)
57 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
57 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
58 option(FSW_stack_report "Enable LFR stack report" OFF)
58 option(FSW_stack_report "Enable LFR stack report" OFF)
59 option(FSW_vhdl_dev "?" OFF)
59 option(FSW_vhdl_dev "?" OFF)
60 option(FSW_lpp_dpu_destid "Set to debug at LPP" ON)
60 option(FSW_lpp_dpu_destid "Set to debug at LPP" ON)
61 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
61 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
62 option(FSW_debug_tch "?" OFF)
62 option(FSW_debug_tch "?" OFF)
63
63
64 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
64 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
65 set(SW_VERSION_N2 "1" CACHE STRING "Choose N2 FSW Version." FORCE)
65 set(SW_VERSION_N2 "1" CACHE STRING "Choose N2 FSW Version." FORCE)
66 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
66 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
67 set(SW_VERSION_N4 "4" CACHE STRING "Choose N4 FSW Version." FORCE)
67 set(SW_VERSION_N4 "5" CACHE STRING "Choose N4 FSW Version." FORCE)
68
69
68
70 if(FSW_verbose)
69 if(FSW_verbose)
71 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
70 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
72 endif()
71 endif()
73 if(FSW_boot_messages)
72 if(FSW_boot_messages)
74 add_definitions(-DBOOT_MESSAGES)
73 add_definitions(-DBOOT_MESSAGES)
75 endif()
74 endif()
76 if(FSW_debug_messages)
75 if(FSW_debug_messages)
77 add_definitions(-DDEBUG_MESSAGES)
76 add_definitions(-DDEBUG_MESSAGES)
78 endif()
77 endif()
79 if(FSW_cpu_usage_report)
78 if(FSW_cpu_usage_report)
80 add_definitions(-DPRINT_TASK_STATISTICS)
79 add_definitions(-DPRINT_TASK_STATISTICS)
81 endif()
80 endif()
82 if(FSW_stack_report)
81 if(FSW_stack_report)
83 add_definitions(-DPRINT_STACK_REPORT)
82 add_definitions(-DPRINT_STACK_REPORT)
84 endif()
83 endif()
85 if(FSW_vhdl_dev)
84 if(FSW_vhdl_dev)
86 add_definitions(-DVHDL_DEV)
85 add_definitions(-DVHDL_DEV)
87 endif()
86 endif()
88 if(FSW_lpp_dpu_destid)
87 if(FSW_lpp_dpu_destid)
89 add_definitions(-DLPP_DPU_DESTID)
88 add_definitions(-DLPP_DPU_DESTID)
90 endif()
89 endif()
91 if(FSW_debug_watchdog)
90 if(FSW_debug_watchdog)
92 add_definitions(-DDEBUG_WATCHDOG)
91 add_definitions(-DDEBUG_WATCHDOG)
93 endif()
92 endif()
94 if(FSW_debug_tch)
93 if(FSW_debug_tch)
95 add_definitions(-DDEBUG_TCH)
94 add_definitions(-DDEBUG_TCH)
96 endif()
95 endif()
97
96
98 add_definitions(-DMSB_FIRST_TCH)
97 add_definitions(-DMSB_FIRST_TCH)
99
98
100 add_definitions(-DSWVERSION=-1-0)
99 add_definitions(-DSWVERSION=-1-0)
101 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
100 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
102 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
101 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
103 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
102 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
104 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
103 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
105
104
106 add_executable(fsw ${SOURCES})
105 add_executable(fsw ${SOURCES})
107 add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE)
106 add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE)
108
107
@@ -1,945 +1,945
1 /** This is the RTEMS initialization module.
1 /** This is the RTEMS initialization module.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 * This module contains two very different information:
6 * This module contains two very different information:
7 * - specific instructions to configure the compilation of the RTEMS executive
7 * - specific instructions to configure the compilation of the RTEMS executive
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
9 *
9 *
10 */
10 */
11
11
12 //*************************
12 //*************************
13 // GPL reminder to be added
13 // GPL reminder to be added
14 //*************************
14 //*************************
15
15
16 #include <rtems.h>
16 #include <rtems.h>
17
17
18 /* configuration information */
18 /* configuration information */
19
19
20 #define CONFIGURE_INIT
20 #define CONFIGURE_INIT
21
21
22 #include <bsp.h> /* for device driver prototypes */
22 #include <bsp.h> /* for device driver prototypes */
23
23
24 /* configuration information */
24 /* configuration information */
25
25
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
28
28
29 #define CONFIGURE_MAXIMUM_TASKS 20
29 #define CONFIGURE_MAXIMUM_TASKS 20
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
37 #define CONFIGURE_MAXIMUM_PERIODS 5
37 #define CONFIGURE_MAXIMUM_PERIODS 5
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [link] [spacewire_reset_link]
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [link] [spacewire_reset_link]
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
40 #ifdef PRINT_STACK_REPORT
40 #ifdef PRINT_STACK_REPORT
41 #define CONFIGURE_STACK_CHECKER_ENABLED
41 #define CONFIGURE_STACK_CHECKER_ENABLED
42 #endif
42 #endif
43
43
44 #include <rtems/confdefs.h>
44 #include <rtems/confdefs.h>
45
45
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
47 #ifdef RTEMS_DRVMGR_STARTUP
47 #ifdef RTEMS_DRVMGR_STARTUP
48 #ifdef LEON3
48 #ifdef LEON3
49 /* Add Timer and UART Driver */
49 /* Add Timer and UART Driver */
50
50
51 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
51 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
52 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
52 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
53 #endif
53 #endif
54
54
55 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
55 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
56 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
56 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
57 #endif
57 #endif
58
58
59 #endif
59 #endif
60 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
60 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
61
61
62 #include <drvmgr/drvmgr_confdefs.h>
62 #include <drvmgr/drvmgr_confdefs.h>
63 #endif
63 #endif
64
64
65 #include "fsw_init.h"
65 #include "fsw_init.h"
66 #include "fsw_config.c"
66 #include "fsw_config.c"
67 #include "GscMemoryLPP.hpp"
67 #include "GscMemoryLPP.hpp"
68
68
69 void initCache()
69 void initCache()
70 {
70 {
71 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
71 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
72 // These should only be read and written using 32-bit LDA/STA instructions.
72 // These should only be read and written using 32-bit LDA/STA instructions.
73 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
73 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
74 // The table below shows the register addresses:
74 // The table below shows the register addresses:
75 // 0x00 Cache control register
75 // 0x00 Cache control register
76 // 0x04 Reserved
76 // 0x04 Reserved
77 // 0x08 Instruction cache configuration register
77 // 0x08 Instruction cache configuration register
78 // 0x0C Data cache configuration register
78 // 0x0C Data cache configuration register
79
79
80 // Cache Control Register Leon3 / Leon3FT
80 // Cache Control Register Leon3 / Leon3FT
81 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
81 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
82 // RFT PS TB DS FD FI FT ST IB
82 // RFT PS TB DS FD FI FT ST IB
83 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
83 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
84 // IP DP ITE IDE DTE DDE DF IF DCS ICS
84 // IP DP ITE IDE DTE DDE DF IF DCS ICS
85
85
86 unsigned int cacheControlRegister;
86 unsigned int cacheControlRegister;
87
87
88 CCR_resetCacheControlRegister();
88 CCR_resetCacheControlRegister();
89 ASR16_resetRegisterProtectionControlRegister();
89 ASR16_resetRegisterProtectionControlRegister();
90
90
91 cacheControlRegister = CCR_getValue();
91 cacheControlRegister = CCR_getValue();
92 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
92 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
93 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
93 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
94
94
95 CCR_enableInstructionCache(); // ICS bits
95 CCR_enableInstructionCache(); // ICS bits
96 CCR_enableDataCache(); // DCS bits
96 CCR_enableDataCache(); // DCS bits
97 CCR_enableInstructionBurstFetch(); // IB bit
97 CCR_enableInstructionBurstFetch(); // IB bit
98
98
99 faultTolerantScheme();
99 faultTolerantScheme();
100
100
101 cacheControlRegister = CCR_getValue();
101 cacheControlRegister = CCR_getValue();
102 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
102 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
103 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
103 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
104
104
105 PRINTF("\n");
105 PRINTF("\n");
106 }
106 }
107
107
108 rtems_task Init( rtems_task_argument ignored )
108 rtems_task Init( rtems_task_argument ignored )
109 {
109 {
110 /** This is the RTEMS INIT taks, it is the first task launched by the system.
110 /** This is the RTEMS INIT taks, it is the first task launched by the system.
111 *
111 *
112 * @param unused is the starting argument of the RTEMS task
112 * @param unused is the starting argument of the RTEMS task
113 *
113 *
114 * The INIT task create and run all other RTEMS tasks.
114 * The INIT task create and run all other RTEMS tasks.
115 *
115 *
116 */
116 */
117
117
118 //***********
118 //***********
119 // INIT CACHE
119 // INIT CACHE
120
120
121 unsigned char *vhdlVersion;
121 unsigned char *vhdlVersion;
122
122
123 reset_lfr();
123 reset_lfr();
124
124
125 reset_local_time();
125