##// END OF EJS Templates
Snapshot resynchro modified
paul -
r267:3616e7d285c0 R3a
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@@ -1,2 +1,2
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
2 b0e42058c39c77fc42a5bd3bf529e4547497c4c3 header/lfr_common_headers
2 449d1ebc41af2e62571508883dab8043a33f16df header/lfr_common_headers
@@ -1,124 +1,124
1 TEMPLATE = app
1 TEMPLATE = app
2 # CONFIG += console v8 sim
2 # CONFIG += console v8 sim
3 # CONFIG options =
3 # CONFIG options =
4 # verbose
4 # verbose
5 # boot_messages
5 # boot_messages
6 # debug_messages
6 # debug_messages
7 # cpu_usage_report
7 # cpu_usage_report
8 # stack_report
8 # stack_report
9 # vhdl_dev
9 # vhdl_dev
10 # debug_tch
10 # debug_tch
11 # lpp_dpu_destid /!\ REMOVE BEFORE DELIVERY TO LESIA /!\
11 # lpp_dpu_destid /!\ REMOVE BEFORE DELIVERY TO LESIA /!\
12 # debug_watchdog
12 # debug_watchdog
13 CONFIG += console verbose lpp_dpu_destid
13 CONFIG += console verbose lpp_dpu_destid
14 CONFIG -= qt
14 CONFIG -= qt
15
15
16 include(./sparc.pri)
16 include(./sparc.pri)
17
17
18 # flight software version
18 # flight software version
19 SWVERSION=-1-0
19 SWVERSION=-1-0
20 DEFINES += SW_VERSION_N1=3 # major
20 DEFINES += SW_VERSION_N1=3 # major
21 DEFINES += SW_VERSION_N2=0 # minor
21 DEFINES += SW_VERSION_N2=0 # minor
22 DEFINES += SW_VERSION_N3=0 # patch
22 DEFINES += SW_VERSION_N3=0 # patch
23 DEFINES += SW_VERSION_N4=16 # internal
23 DEFINES += SW_VERSION_N4=17 # internal
24
24
25 # <GCOV>
25 # <GCOV>
26 #QMAKE_CFLAGS_RELEASE += -fprofile-arcs -ftest-coverage
26 #QMAKE_CFLAGS_RELEASE += -fprofile-arcs -ftest-coverage
27 #LIBS += -lgcov /opt/GCOV/01A/lib/overload.o -lc
27 #LIBS += -lgcov /opt/GCOV/01A/lib/overload.o -lc
28 # </GCOV>
28 # </GCOV>
29
29
30 # <CHANGE BEFORE FLIGHT>
30 # <CHANGE BEFORE FLIGHT>
31 contains( CONFIG, lpp_dpu_destid ) {
31 contains( CONFIG, lpp_dpu_destid ) {
32 DEFINES += LPP_DPU_DESTID
32 DEFINES += LPP_DPU_DESTID
33 }
33 }
34 # </CHANGE BEFORE FLIGHT>
34 # </CHANGE BEFORE FLIGHT>
35
35
36 contains( CONFIG, debug_tch ) {
36 contains( CONFIG, debug_tch ) {
37 DEFINES += DEBUG_TCH
37 DEFINES += DEBUG_TCH
38 }
38 }
39 DEFINES += MSB_FIRST_TCH
39 DEFINES += MSB_FIRST_TCH
40
40
41 contains( CONFIG, vhdl_dev ) {
41 contains( CONFIG, vhdl_dev ) {
42 DEFINES += VHDL_DEV
42 DEFINES += VHDL_DEV
43 }
43 }
44
44
45 contains( CONFIG, verbose ) {
45 contains( CONFIG, verbose ) {
46 DEFINES += PRINT_MESSAGES_ON_CONSOLE
46 DEFINES += PRINT_MESSAGES_ON_CONSOLE
47 }
47 }
48
48
49 contains( CONFIG, debug_messages ) {
49 contains( CONFIG, debug_messages ) {
50 DEFINES += DEBUG_MESSAGES
50 DEFINES += DEBUG_MESSAGES
51 }
51 }
52
52
53 contains( CONFIG, cpu_usage_report ) {
53 contains( CONFIG, cpu_usage_report ) {
54 DEFINES += PRINT_TASK_STATISTICS
54 DEFINES += PRINT_TASK_STATISTICS
55 }
55 }
56
56
57 contains( CONFIG, stack_report ) {
57 contains( CONFIG, stack_report ) {
58 DEFINES += PRINT_STACK_REPORT
58 DEFINES += PRINT_STACK_REPORT
59 }
59 }
60
60
61 contains( CONFIG, boot_messages ) {
61 contains( CONFIG, boot_messages ) {
62 DEFINES += BOOT_MESSAGES
62 DEFINES += BOOT_MESSAGES
63 }
63 }
64
64
65 contains( CONFIG, debug_watchdog ) {
65 contains( CONFIG, debug_watchdog ) {
66 DEFINES += DEBUG_WATCHDOG
66 DEFINES += DEBUG_WATCHDOG
67 }
67 }
68
68
69 #doxygen.target = doxygen
69 #doxygen.target = doxygen
70 #doxygen.commands = doxygen ../doc/Doxyfile
70 #doxygen.commands = doxygen ../doc/Doxyfile
71 #QMAKE_EXTRA_TARGETS += doxygen
71 #QMAKE_EXTRA_TARGETS += doxygen
72
72
73 TARGET = fsw
73 TARGET = fsw
74
74
75 INCLUDEPATH += \
75 INCLUDEPATH += \
76 $${PWD}/../src \
76 $${PWD}/../src \
77 $${PWD}/../header \
77 $${PWD}/../header \
78 $${PWD}/../header/lfr_common_headers \
78 $${PWD}/../header/lfr_common_headers \
79 $${PWD}/../header/processing \
79 $${PWD}/../header/processing \
80 $${PWD}/../LFR_basic-parameters
80 $${PWD}/../LFR_basic-parameters
81
81
82 SOURCES += \
82 SOURCES += \
83 ../src/wf_handler.c \
83 ../src/wf_handler.c \
84 ../src/tc_handler.c \
84 ../src/tc_handler.c \
85 ../src/fsw_misc.c \
85 ../src/fsw_misc.c \
86 ../src/fsw_init.c \
86 ../src/fsw_init.c \
87 ../src/fsw_globals.c \
87 ../src/fsw_globals.c \
88 ../src/fsw_spacewire.c \
88 ../src/fsw_spacewire.c \
89 ../src/tc_load_dump_parameters.c \
89 ../src/tc_load_dump_parameters.c \
90 ../src/tm_lfr_tc_exe.c \
90 ../src/tm_lfr_tc_exe.c \
91 ../src/tc_acceptance.c \
91 ../src/tc_acceptance.c \
92 ../src/processing/fsw_processing.c \
92 ../src/processing/fsw_processing.c \
93 ../src/processing/avf0_prc0.c \
93 ../src/processing/avf0_prc0.c \
94 ../src/processing/avf1_prc1.c \
94 ../src/processing/avf1_prc1.c \
95 ../src/processing/avf2_prc2.c \
95 ../src/processing/avf2_prc2.c \
96 ../src/lfr_cpu_usage_report.c \
96 ../src/lfr_cpu_usage_report.c \
97 ../LFR_basic-parameters/basic_parameters.c
97 ../LFR_basic-parameters/basic_parameters.c
98
98
99 HEADERS += \
99 HEADERS += \
100 ../header/wf_handler.h \
100 ../header/wf_handler.h \
101 ../header/tc_handler.h \
101 ../header/tc_handler.h \
102 ../header/grlib_regs.h \
102 ../header/grlib_regs.h \
103 ../header/fsw_misc.h \
103 ../header/fsw_misc.h \
104 ../header/fsw_init.h \
104 ../header/fsw_init.h \
105 ../header/fsw_spacewire.h \
105 ../header/fsw_spacewire.h \
106 ../header/tc_load_dump_parameters.h \
106 ../header/tc_load_dump_parameters.h \
107 ../header/tm_lfr_tc_exe.h \
107 ../header/tm_lfr_tc_exe.h \
108 ../header/tc_acceptance.h \
108 ../header/tc_acceptance.h \
109 ../header/processing/fsw_processing.h \
109 ../header/processing/fsw_processing.h \
110 ../header/processing/avf0_prc0.h \
110 ../header/processing/avf0_prc0.h \
111 ../header/processing/avf1_prc1.h \
111 ../header/processing/avf1_prc1.h \
112 ../header/processing/avf2_prc2.h \
112 ../header/processing/avf2_prc2.h \
113 ../header/fsw_params_wf_handler.h \
113 ../header/fsw_params_wf_handler.h \
114 ../header/lfr_cpu_usage_report.h \
114 ../header/lfr_cpu_usage_report.h \
115 ../header/lfr_common_headers/ccsds_types.h \
115 ../header/lfr_common_headers/ccsds_types.h \
116 ../header/lfr_common_headers/fsw_params.h \
116 ../header/lfr_common_headers/fsw_params.h \
117 ../header/lfr_common_headers/fsw_params_nb_bytes.h \
117 ../header/lfr_common_headers/fsw_params_nb_bytes.h \
118 ../header/lfr_common_headers/fsw_params_processing.h \
118 ../header/lfr_common_headers/fsw_params_processing.h \
119 ../header/lfr_common_headers/TC_types.h \
119 ../header/lfr_common_headers/TC_types.h \
120 ../header/lfr_common_headers/tm_byte_positions.h \
120 ../header/lfr_common_headers/tm_byte_positions.h \
121 ../LFR_basic-parameters/basic_parameters.h \
121 ../LFR_basic-parameters/basic_parameters.h \
122 ../LFR_basic-parameters/basic_parameters_params.h \
122 ../LFR_basic-parameters/basic_parameters_params.h \
123 ../header/GscMemoryLPP.hpp
123 ../header/GscMemoryLPP.hpp
124
124
@@ -1,138 +1,138
1 #ifndef GRLIB_REGS_H_INCLUDED
1 #ifndef GRLIB_REGS_H_INCLUDED
2 #define GRLIB_REGS_H_INCLUDED
2 #define GRLIB_REGS_H_INCLUDED
3
3
4 #define NB_GPTIMER 3
4 #define NB_GPTIMER 3
5
5
6 struct apbuart_regs_str{
6 struct apbuart_regs_str{
7 volatile unsigned int data;
7 volatile unsigned int data;
8 volatile unsigned int status;
8 volatile unsigned int status;
9 volatile unsigned int ctrl;
9 volatile unsigned int ctrl;
10 volatile unsigned int scaler;
10 volatile unsigned int scaler;
11 volatile unsigned int fifoDebug;
11 volatile unsigned int fifoDebug;
12 };
12 };
13
13
14 struct grgpio_regs_str{
14 struct grgpio_regs_str{
15 volatile int io_port_data_register;
15 volatile int io_port_data_register;
16 int io_port_output_register;
16 int io_port_output_register;
17 int io_port_direction_register;
17 int io_port_direction_register;
18 int interrupt_mak_register;
18 int interrupt_mak_register;
19 int interrupt_polarity_register;
19 int interrupt_polarity_register;
20 int interrupt_edge_register;
20 int interrupt_edge_register;
21 int bypass_register;
21 int bypass_register;
22 int reserved;
22 int reserved;
23 // 0x20-0x3c interrupt map register(s)
23 // 0x20-0x3c interrupt map register(s)
24 };
24 };
25
25
26 typedef struct {
26 typedef struct {
27 volatile unsigned int counter;
27 volatile unsigned int counter;
28 volatile unsigned int reload;
28 volatile unsigned int reload;
29 volatile unsigned int ctrl;
29 volatile unsigned int ctrl;
30 volatile unsigned int unused;
30 volatile unsigned int unused;
31 } timer_regs_t;
31 } timer_regs_t;
32
32
33 typedef struct {
33 typedef struct {
34 volatile unsigned int scaler_value;
34 volatile unsigned int scaler_value;
35 volatile unsigned int scaler_reload;
35 volatile unsigned int scaler_reload;
36 volatile unsigned int conf;
36 volatile unsigned int conf;
37 volatile unsigned int unused0;
37 volatile unsigned int unused0;
38 timer_regs_t timer[NB_GPTIMER];
38 timer_regs_t timer[NB_GPTIMER];
39 } gptimer_regs_t;
39 } gptimer_regs_t;
40
40
41 typedef struct {
41 typedef struct {
42 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
42 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
43 // bit 1 is the soft reset for the time management module
43 // bit 1 is the soft reset for the time management module
44 // bit 2 is the soft reset for the waveform picker and the spectral matrix modules, set to 1 after HW reset
44 // bit 2 is the soft reset for the waveform picker and the spectral matrix modules, set to 1 after HW reset
45 volatile int coarse_time_load;
45 volatile int coarse_time_load;
46 volatile int coarse_time;
46 volatile int coarse_time;
47 volatile int fine_time;
47 volatile int fine_time;
48 // TEMPERATURES
48 // TEMPERATURES
49 volatile int temp_pcb; // SEL1 = 0 SEL0 = 0
49 volatile int temp_pcb; // SEL1 = 0 SEL0 = 0
50 volatile int temp_fpga; // SEL1 = 0 SEL0 = 1
50 volatile int temp_fpga; // SEL1 = 0 SEL0 = 1
51 volatile int temp_scm; // SEL1 = 1 SEL0 = 0
51 volatile int temp_scm; // SEL1 = 1 SEL0 = 0
52 // CALIBRATION
52 // CALIBRATION
53 volatile unsigned int calDACCtrl;
53 volatile unsigned int calDACCtrl;
54 volatile unsigned int calPrescaler;
54 volatile unsigned int calPrescaler;
55 volatile unsigned int calDivisor;
55 volatile unsigned int calDivisor;
56 volatile unsigned int calDataPtr;
56 volatile unsigned int calDataPtr;
57 volatile unsigned int calData;
57 volatile unsigned int calData;
58 } time_management_regs_t;
58 } time_management_regs_t;
59
59
60 // PDB >= 0.1.28, 0x80000f54
60 // PDB >= 0.1.28, 0x80000f54
61 typedef struct{
61 typedef struct{
62 int data_shaping; // 0x00 00 *** R1 R0 SP1 SP0 BW
62 int data_shaping; // 0x00 00 *** R1 R0 SP1 SP0 BW
63 int run_burst_enable; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
63 int run_burst_enable; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
64 int addr_data_f0_0; // 0x08
64 int addr_data_f0_0; // 0x08
65 int addr_data_f0_1; // 0x0c
65 int addr_data_f0_1; // 0x0c
66 int addr_data_f1_0; // 0x10
66 int addr_data_f1_0; // 0x10
67 int addr_data_f1_1; // 0x14
67 int addr_data_f1_1; // 0x14
68 int addr_data_f2_0; // 0x18
68 int addr_data_f2_0; // 0x18
69 int addr_data_f2_1; // 0x1c
69 int addr_data_f2_1; // 0x1c
70 int addr_data_f3_0; // 0x20
70 int addr_data_f3_0; // 0x20
71 int addr_data_f3_1; // 0x24
71 int addr_data_f3_1; // 0x24
72 volatile int status; // 0x28
72 volatile int status; // 0x28
73 int delta_snapshot; // 0x2c
73 volatile int delta_snapshot; // 0x2c
74 int delta_f0; // 0x30
74 int delta_f0; // 0x30
75 int delta_f0_2; // 0x34
75 int delta_f0_2; // 0x34
76 int delta_f1; // 0x38
76 int delta_f1; // 0x38
77 int delta_f2; // 0x3c
77 int delta_f2; // 0x3c
78 int nb_data_by_buffer; // 0x40 number of samples in a buffer = 2688
78 int nb_data_by_buffer; // 0x40 number of samples in a buffer = 2688
79 int snapshot_param; // 0x44
79 int snapshot_param; // 0x44
80 int start_date; // 0x48
80 int start_date; // 0x48
81 //
81 //
82 volatile unsigned int f0_0_coarse_time; // 0x4c
82 volatile unsigned int f0_0_coarse_time; // 0x4c
83 volatile unsigned int f0_0_fine_time; // 0x50
83 volatile unsigned int f0_0_fine_time; // 0x50
84 volatile unsigned int f0_1_coarse_time; // 0x54
84 volatile unsigned int f0_1_coarse_time; // 0x54
85 volatile unsigned int f0_1_fine_time; // 0x58
85 volatile unsigned int f0_1_fine_time; // 0x58
86 //
86 //
87 volatile unsigned int f1_0_coarse_time; // 0x5c
87 volatile unsigned int f1_0_coarse_time; // 0x5c
88 volatile unsigned int f1_0_fine_time; // 0x60
88 volatile unsigned int f1_0_fine_time; // 0x60
89 volatile unsigned int f1_1_coarse_time; // 0x64
89 volatile unsigned int f1_1_coarse_time; // 0x64
90 volatile unsigned int f1_1_fine_time; // 0x68
90 volatile unsigned int f1_1_fine_time; // 0x68
91 //
91 //
92 volatile unsigned int f2_0_coarse_time; // 0x6c
92 volatile unsigned int f2_0_coarse_time; // 0x6c
93 volatile unsigned int f2_0_fine_time; // 0x70
93 volatile unsigned int f2_0_fine_time; // 0x70
94 volatile unsigned int f2_1_coarse_time; // 0x74
94 volatile unsigned int f2_1_coarse_time; // 0x74
95 volatile unsigned int f2_1_fine_time; // 0x78
95 volatile unsigned int f2_1_fine_time; // 0x78
96 //
96 //
97 volatile unsigned int f3_0_coarse_time; // 0x7c => 0x7c + 0xf54 = 0xd0
97 volatile unsigned int f3_0_coarse_time; // 0x7c => 0x7c + 0xf54 = 0xd0
98 volatile unsigned int f3_0_fine_time; // 0x80
98 volatile unsigned int f3_0_fine_time; // 0x80
99 volatile unsigned int f3_1_coarse_time; // 0x84
99 volatile unsigned int f3_1_coarse_time; // 0x84
100 volatile unsigned int f3_1_fine_time; // 0x88
100 volatile unsigned int f3_1_fine_time; // 0x88
101 //
101 //
102 unsigned int buffer_length; // 0x8c = buffer length in burst 2688 / 16 = 168
102 unsigned int buffer_length; // 0x8c = buffer length in burst 2688 / 16 = 168
103 //
103 //
104 volatile unsigned int v; // 0x90
104 volatile unsigned int v; // 0x90
105 volatile unsigned int e1; // 0x94
105 volatile unsigned int e1; // 0x94
106 volatile unsigned int e2; // 0x98
106 volatile unsigned int e2; // 0x98
107 } waveform_picker_regs_0_1_18_t;
107 } waveform_picker_regs_0_1_18_t;
108
108
109 typedef struct {
109 typedef struct {
110 volatile int config; // 0x00
110 volatile int config; // 0x00
111 volatile int status; // 0x04
111 volatile int status; // 0x04
112 volatile int f0_0_address; // 0x08
112 volatile int f0_0_address; // 0x08
113 volatile int f0_1_address; // 0x0C
113 volatile int f0_1_address; // 0x0C
114 //
114 //
115 volatile int f1_0_address; // 0x10
115 volatile int f1_0_address; // 0x10
116 volatile int f1_1_address; // 0x14
116 volatile int f1_1_address; // 0x14
117 volatile int f2_0_address; // 0x18
117 volatile int f2_0_address; // 0x18
118 volatile int f2_1_address; // 0x1C
118 volatile int f2_1_address; // 0x1C
119 //
119 //
120 volatile unsigned int f0_0_coarse_time; // 0x20
120 volatile unsigned int f0_0_coarse_time; // 0x20
121 volatile unsigned int f0_0_fine_time; // 0x24
121 volatile unsigned int f0_0_fine_time; // 0x24
122 volatile unsigned int f0_1_coarse_time; // 0x28
122 volatile unsigned int f0_1_coarse_time; // 0x28
123 volatile unsigned int f0_1_fine_time; // 0x2C
123 volatile unsigned int f0_1_fine_time; // 0x2C
124 //
124 //
125 volatile unsigned int f1_0_coarse_time; // 0x30
125 volatile unsigned int f1_0_coarse_time; // 0x30
126 volatile unsigned int f1_0_fine_time; // 0x34
126 volatile unsigned int f1_0_fine_time; // 0x34
127 volatile unsigned int f1_1_coarse_time; // 0x38
127 volatile unsigned int f1_1_coarse_time; // 0x38
128 volatile unsigned int f1_1_fine_time; // 0x3C
128 volatile unsigned int f1_1_fine_time; // 0x3C
129 //
129 //
130 volatile unsigned int f2_0_coarse_time; // 0x40
130 volatile unsigned int f2_0_coarse_time; // 0x40
131 volatile unsigned int f2_0_fine_time; // 0x44
131 volatile unsigned int f2_0_fine_time; // 0x44
132 volatile unsigned int f2_1_coarse_time; // 0x48
132 volatile unsigned int f2_1_coarse_time; // 0x48
133 volatile unsigned int f2_1_fine_time; // 0x4C
133 volatile unsigned int f2_1_fine_time; // 0x4C
134 //
134 //
135 unsigned int matrix_length; // 0x50, length of a spectral matrix in burst 3200 / 16 = 200 = 0xc8
135 unsigned int matrix_length; // 0x50, length of a spectral matrix in burst 3200 / 16 = 200 = 0xc8
136 } spectral_matrix_regs_t;
136 } spectral_matrix_regs_t;
137
137
138 #endif // GRLIB_REGS_H_INCLUDED
138 #endif // GRLIB_REGS_H_INCLUDED
@@ -1,916 +1,917
1 /** This is the RTEMS initialization module.
1 /** This is the RTEMS initialization module.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 * This module contains two very different information:
6 * This module contains two very different information:
7 * - specific instructions to configure the compilation of the RTEMS executive
7 * - specific instructions to configure the compilation of the RTEMS executive
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
9 *
9 *
10 */
10 */
11
11
12 //*************************
12 //*************************
13 // GPL reminder to be added
13 // GPL reminder to be added
14 //*************************
14 //*************************
15
15
16 #include <rtems.h>
16 #include <rtems.h>
17
17
18 /* configuration information */
18 /* configuration information */
19
19
20 #define CONFIGURE_INIT
20 #define CONFIGURE_INIT
21
21
22 #include <bsp.h> /* for device driver prototypes */
22 #include <bsp.h> /* for device driver prototypes */
23
23
24 /* configuration information */
24 /* configuration information */
25
25
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
28
28
29 #define CONFIGURE_MAXIMUM_TASKS 20
29 #define CONFIGURE_MAXIMUM_TASKS 20
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
37 #define CONFIGURE_MAXIMUM_PERIODS 5
37 #define CONFIGURE_MAXIMUM_PERIODS 5
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [link] [spacewire_reset_link]
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [link] [spacewire_reset_link]
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
40 #ifdef PRINT_STACK_REPORT
40 #ifdef PRINT_STACK_REPORT
41 #define CONFIGURE_STACK_CHECKER_ENABLED
41 #define CONFIGURE_STACK_CHECKER_ENABLED
42 #endif
42 #endif
43
43
44 #include <rtems/confdefs.h>
44 #include <rtems/confdefs.h>
45
45
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
47 #ifdef RTEMS_DRVMGR_STARTUP
47 #ifdef RTEMS_DRVMGR_STARTUP
48 #ifdef LEON3
48 #ifdef LEON3
49 /* Add Timer and UART Driver */
49 /* Add Timer and UART Driver */
50 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
50 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
51 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
51 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
52 #endif
52 #endif
53 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
53 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
54 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
54 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
55 #endif
55 #endif
56 #endif
56 #endif
57 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
57 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
58 #include <drvmgr/drvmgr_confdefs.h>
58 #include <drvmgr/drvmgr_confdefs.h>
59 #endif
59 #endif
60
60
61 #include "fsw_init.h"
61 #include "fsw_init.h"
62 #include "fsw_config.c"
62 #include "fsw_config.c"
63 #include "GscMemoryLPP.hpp"
63 #include "GscMemoryLPP.hpp"
64
64
65 void initCache()
65 void initCache()
66 {
66 {
67 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
67 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
68 // These should only be read and written using 32-bit LDA/STA instructions.
68 // These should only be read and written using 32-bit LDA/STA instructions.
69 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
69 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
70 // The table below shows the register addresses:
70 // The table below shows the register addresses:
71 // 0x00 Cache control register
71 // 0x00 Cache control register
72 // 0x04 Reserved
72 // 0x04 Reserved
73 // 0x08 Instruction cache configuration register
73 // 0x08 Instruction cache configuration register
74 // 0x0C Data cache configuration register
74 // 0x0C Data cache configuration register
75
75
76 // Cache Control Register Leon3 / Leon3FT
76 // Cache Control Register Leon3 / Leon3FT
77 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
77 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
78 // RFT PS TB DS FD FI FT ST IB
78 // RFT PS TB DS FD FI FT ST IB
79 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
79 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
80 // IP DP ITE IDE DTE DDE DF IF DCS ICS
80 // IP DP ITE IDE DTE DDE DF IF DCS ICS
81
81
82 unsigned int cacheControlRegister;
82 unsigned int cacheControlRegister;
83
83
84 CCR_resetCacheControlRegister();
84 CCR_resetCacheControlRegister();
85 ASR16_resetRegisterProtectionControlRegister();
85 ASR16_resetRegisterProtectionControlRegister();
86
86
87 cacheControlRegister = CCR_getValue();
87 cacheControlRegister = CCR_getValue();
88 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
88 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
89 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
89 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
90
90
91 CCR_enableInstructionCache(); // ICS bits
91 CCR_enableInstructionCache(); // ICS bits
92 CCR_enableDataCache(); // DCS bits
92 CCR_enableDataCache(); // DCS bits
93 CCR_enableInstructionBurstFetch(); // IB bit
93 CCR_enableInstructionBurstFetch(); // IB bit
94
94
95 faultTolerantScheme();
95 faultTolerantScheme();
96
96
97 cacheControlRegister = CCR_getValue();
97 cacheControlRegister = CCR_getValue();
98 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
98 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
99 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
99 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
100
100
101 PRINTF("\n");
101 PRINTF("\n");
102 }
102 }
103
103
104 rtems_task Init( rtems_task_argument ignored )
104 rtems_task Init( rtems_task_argument ignored )
105 {
105 {
106 /** This is the RTEMS INIT taks, it is the first task launched by the system.
106 /** This is the RTEMS INIT taks, it is the first task launched by the system.
107 *
107 *
108 * @param unused is the starting argument of the RTEMS task
108 * @param unused is the starting argument of the RTEMS task
109 *
109 *
110 * The INIT task create and run all other RTEMS tasks.
110 * The INIT task create and run all other RTEMS tasks.
111 *
111 *
112 */
112 */
113
113
114 //***********
114 //***********
115 // INIT CACHE
115 // INIT CACHE
116
116
117 unsigned char *vhdlVersion;
117 unsigned char *vhdlVersion;
118
118
119 reset_lfr();
119 reset_lfr();
120
120
121 reset_local_time();
121 reset_local_time();
122
122
123 rtems_cpu_usage_reset();
123 rtems_cpu_usage_reset();
124
124
125 rtems_status_code status;
125 rtems_status_code status;
126 rtems_status_code status_spw;
126 rtems_status_code status_spw;
127 rtems_isr_entry old_isr_handler;
127 rtems_isr_entry old_isr_handler;
128
128
129 // UART settings
129 // UART settings
130 enable_apbuart_transmitter();
130 enable_apbuart_transmitter();
131 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
131 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
132
132
133 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
133 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
134
134
135
135
136 PRINTF("\n\n\n\n\n")
136 PRINTF("\n\n\n\n\n")
137
137
138 initCache();
138 initCache();
139
139
140 PRINTF("*************************\n")
140 PRINTF("*************************\n")
141 PRINTF("** LFR Flight Software **\n")
141 PRINTF("** LFR Flight Software **\n")
142 PRINTF1("** %d.", SW_VERSION_N1)
142 PRINTF1("** %d.", SW_VERSION_N1)
143 PRINTF1("%d." , SW_VERSION_N2)
143 PRINTF1("%d." , SW_VERSION_N2)
144 PRINTF1("%d." , SW_VERSION_N3)
144 PRINTF1("%d." , SW_VERSION_N3)
145 PRINTF1("%d **\n", SW_VERSION_N4)
145 PRINTF1("%d **\n", SW_VERSION_N4)
146
146
147 vhdlVersion = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
147 vhdlVersion = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
148 PRINTF("** VHDL **\n")
148 PRINTF("** VHDL **\n")
149 PRINTF1("** %d.", vhdlVersion[1])
149 PRINTF1("** %d.", vhdlVersion[1])
150 PRINTF1("%d." , vhdlVersion[2])
150 PRINTF1("%d." , vhdlVersion[2])
151 PRINTF1("%d **\n", vhdlVersion[3])
151 PRINTF1("%d **\n", vhdlVersion[3])
152 PRINTF("*************************\n")
152 PRINTF("*************************\n")
153 PRINTF("\n\n")
153 PRINTF("\n\n")
154
154
155 init_parameter_dump();
155 init_parameter_dump();
156 init_kcoefficients_dump();
156 init_kcoefficients_dump();
157 init_local_mode_parameters();
157 init_local_mode_parameters();
158 init_housekeeping_parameters();
158 init_housekeeping_parameters();
159 init_k_coefficients_prc0();
159 init_k_coefficients_prc0();
160 init_k_coefficients_prc1();
160 init_k_coefficients_prc1();
161 init_k_coefficients_prc2();
161 init_k_coefficients_prc2();
162 pa_bia_status_info = 0x00;
162 pa_bia_status_info = 0x00;
163 update_last_valid_transition_date( DEFAULT_LAST_VALID_TRANSITION_DATE );
163 update_last_valid_transition_date( DEFAULT_LAST_VALID_TRANSITION_DATE );
164
164
165 // waveform picker initialization
165 // waveform picker initialization
166 WFP_init_rings(); LEON_Clear_interrupt( IRQ_SPARC_GPTIMER_WATCHDOG ); // initialize the waveform rings
166 WFP_init_rings(); LEON_Clear_interrupt( IRQ_SPARC_GPTIMER_WATCHDOG ); // initialize the waveform rings
167 WFP_reset_current_ring_nodes();
167 WFP_reset_current_ring_nodes();
168 reset_waveform_picker_regs();
168 reset_waveform_picker_regs();
169
169
170 // spectral matrices initialization
170 // spectral matrices initialization
171 SM_init_rings(); // initialize spectral matrices rings
171 SM_init_rings(); // initialize spectral matrices rings
172 SM_reset_current_ring_nodes();
172 SM_reset_current_ring_nodes();
173 reset_spectral_matrix_regs();
173 reset_spectral_matrix_regs();
174
174
175 // configure calibration
175 // configure calibration
176 configureCalibration( false ); // true means interleaved mode, false is for normal mode
176 configureCalibration( false ); // true means interleaved mode, false is for normal mode
177
177
178 updateLFRCurrentMode( LFR_MODE_STANDBY );
178 updateLFRCurrentMode( LFR_MODE_STANDBY );
179
179
180 BOOT_PRINTF1("in INIT *** lfrCurrentMode is %d\n", lfrCurrentMode)
180 BOOT_PRINTF1("in INIT *** lfrCurrentMode is %d\n", lfrCurrentMode)
181
181
182 create_names(); // create all names
182 create_names(); // create all names
183
183
184 status = create_timecode_timer(); // create the timer used by timecode_irq_handler
184 status = create_timecode_timer(); // create the timer used by timecode_irq_handler
185 if (status != RTEMS_SUCCESSFUL)
185 if (status != RTEMS_SUCCESSFUL)
186 {
186 {
187 PRINTF1("in INIT *** ERR in create_timer_timecode, code %d", status)
187 PRINTF1("in INIT *** ERR in create_timer_timecode, code %d", status)
188 }
188 }
189
189
190 status = create_message_queues(); // create message queues
190 status = create_message_queues(); // create message queues
191 if (status != RTEMS_SUCCESSFUL)
191 if (status != RTEMS_SUCCESSFUL)
192 {
192 {
193 PRINTF1("in INIT *** ERR in create_message_queues, code %d", status)
193 PRINTF1("in INIT *** ERR in create_message_queues, code %d", status)
194 }
194 }
195
195
196 status = create_all_tasks(); // create all tasks
196 status = create_all_tasks(); // create all tasks
197 if (status != RTEMS_SUCCESSFUL)
197 if (status != RTEMS_SUCCESSFUL)
198 {
198 {
199 PRINTF1("in INIT *** ERR in create_all_tasks, code %d\n", status)
199 PRINTF1("in INIT *** ERR in create_all_tasks, code %d\n", status)
200 }
200 }
201
201
202 // **************************
202 // **************************
203 // <SPACEWIRE INITIALIZATION>
203 // <SPACEWIRE INITIALIZATION>
204 status_spw = spacewire_open_link(); // (1) open the link
204 status_spw = spacewire_open_link(); // (1) open the link
205 if ( status_spw != RTEMS_SUCCESSFUL )
205 if ( status_spw != RTEMS_SUCCESSFUL )
206 {
206 {
207 PRINTF1("in INIT *** ERR spacewire_open_link code %d\n", status_spw )
207 PRINTF1("in INIT *** ERR spacewire_open_link code %d\n", status_spw )
208 }
208 }
209
209
210 if ( status_spw == RTEMS_SUCCESSFUL ) // (2) configure the link
210 if ( status_spw == RTEMS_SUCCESSFUL ) // (2) configure the link
211 {
211 {
212 status_spw = spacewire_configure_link( fdSPW );
212 status_spw = spacewire_configure_link( fdSPW );
213 if ( status_spw != RTEMS_SUCCESSFUL )
213 if ( status_spw != RTEMS_SUCCESSFUL )
214 {
214 {
215 PRINTF1("in INIT *** ERR spacewire_configure_link code %d\n", status_spw )
215 PRINTF1("in INIT *** ERR spacewire_configure_link code %d\n", status_spw )
216 }
216 }
217 }
217 }
218
218
219 if ( status_spw == RTEMS_SUCCESSFUL) // (3) start the link
219 if ( status_spw == RTEMS_SUCCESSFUL) // (3) start the link
220 {
220 {
221 status_spw = spacewire_start_link( fdSPW );
221 status_spw = spacewire_start_link( fdSPW );
222 if ( status_spw != RTEMS_SUCCESSFUL )
222 if ( status_spw != RTEMS_SUCCESSFUL )
223 {
223 {
224 PRINTF1("in INIT *** ERR spacewire_start_link code %d\n", status_spw )
224 PRINTF1("in INIT *** ERR spacewire_start_link code %d\n", status_spw )
225 }
225 }
226 }
226 }
227 // </SPACEWIRE INITIALIZATION>
227 // </SPACEWIRE INITIALIZATION>
228 // ***************************
228 // ***************************
229
229
230 status = start_all_tasks(); // start all tasks
230 status = start_all_tasks(); // start all tasks
231 if (status != RTEMS_SUCCESSFUL)
231 if (status != RTEMS_SUCCESSFUL)
232 {
232 {
233 PRINTF1("in INIT *** ERR in start_all_tasks, code %d", status)
233 PRINTF1("in INIT *** ERR in start_all_tasks, code %d", status)
234 }
234 }
235
235
236 // start RECV and SEND *AFTER* SpaceWire Initialization, due to the timeout of the start call during the initialization
236 // start RECV and SEND *AFTER* SpaceWire Initialization, due to the timeout of the start call during the initialization
237 status = start_recv_send_tasks();
237 status = start_recv_send_tasks();
238 if ( status != RTEMS_SUCCESSFUL )
238 if ( status != RTEMS_SUCCESSFUL )
239 {
239 {
240 PRINTF1("in INIT *** ERR start_recv_send_tasks code %d\n", status )
240 PRINTF1("in INIT *** ERR start_recv_send_tasks code %d\n", status )
241 }
241 }
242
242
243 // suspend science tasks, they will be restarted later depending on the mode
243 // suspend science tasks, they will be restarted later depending on the mode
244 status = suspend_science_tasks(); // suspend science tasks (not done in stop_current_mode if current mode = STANDBY)
244 status = suspend_science_tasks(); // suspend science tasks (not done in stop_current_mode if current mode = STANDBY)
245 if (status != RTEMS_SUCCESSFUL)
245 if (status != RTEMS_SUCCESSFUL)
246 {
246 {
247 PRINTF1("in INIT *** in suspend_science_tasks *** ERR code: %d\n", status)
247 PRINTF1("in INIT *** in suspend_science_tasks *** ERR code: %d\n", status)
248 }
248 }
249
249
250 // configure IRQ handling for the waveform picker unit
250 // configure IRQ handling for the waveform picker unit
251 status = rtems_interrupt_catch( waveforms_isr,
251 status = rtems_interrupt_catch( waveforms_isr,
252 IRQ_SPARC_WAVEFORM_PICKER,
252 IRQ_SPARC_WAVEFORM_PICKER,
253 &old_isr_handler) ;
253 &old_isr_handler) ;
254 // configure IRQ handling for the spectral matrices unit
254 // configure IRQ handling for the spectral matrices unit
255 status = rtems_interrupt_catch( spectral_matrices_isr,
255 status = rtems_interrupt_catch( spectral_matrices_isr,
256 IRQ_SPARC_SPECTRAL_MATRIX,
256 IRQ_SPARC_SPECTRAL_MATRIX,
257 &old_isr_handler) ;
257 &old_isr_handler) ;
258
258
259 // if the spacewire link is not up then send an event to the SPIQ task for link recovery
259 // if the spacewire link is not up then send an event to the SPIQ task for link recovery
260 if ( status_spw != RTEMS_SUCCESSFUL )
260 if ( status_spw != RTEMS_SUCCESSFUL )
261 {
261 {
262 status = rtems_event_send( Task_id[TASKID_SPIQ], SPW_LINKERR_EVENT );
262 status = rtems_event_send( Task_id[TASKID_SPIQ], SPW_LINKERR_EVENT );
263 if ( status != RTEMS_SUCCESSFUL ) {
263 if ( status != RTEMS_SUCCESSFUL ) {
264 PRINTF1("in INIT *** ERR rtems_event_send to SPIQ code %d\n", status )
264 PRINTF1("in INIT *** ERR rtems_event_send to SPIQ code %d\n", status )
265 }
265 }
266 }
266 }
267
267
268 BOOT_PRINTF("delete INIT\n")
268 BOOT_PRINTF("delete INIT\n")
269
269
270 set_hk_lfr_sc_potential_flag( true );
270 set_hk_lfr_sc_potential_flag( true );
271
271
272 // start the timer to detect a missing spacewire timecode
272 // start the timer to detect a missing spacewire timecode
273 // the timeout is larger because the spw IP needs to receive several valid timecodes before generating a tickout
273 // the timeout is larger because the spw IP needs to receive several valid timecodes before generating a tickout
274 // if a tickout is generated, the timer is restarted
274 // if a tickout is generated, the timer is restarted
275 status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT_INIT, timecode_timer_routine, NULL );
275 status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT_INIT, timecode_timer_routine, NULL );
276
276 grspw_timecode_callback = &timecode_irq_handler;
277 grspw_timecode_callback = &timecode_irq_handler;
277
278
278 status = rtems_task_delete(RTEMS_SELF);
279 status = rtems_task_delete(RTEMS_SELF);
279
280
280 }
281 }
281
282
282 void init_local_mode_parameters( void )
283 void init_local_mode_parameters( void )
283 {
284 {
284 /** This function initialize the param_local global variable with default values.
285 /** This function initialize the param_local global variable with default values.
285 *
286 *
286 */
287 */
287
288
288 unsigned int i;
289 unsigned int i;
289
290
290 // LOCAL PARAMETERS
291 // LOCAL PARAMETERS
291
292
292 BOOT_PRINTF1("local_sbm1_nb_cwf_max %d \n", param_local.local_sbm1_nb_cwf_max)
293 BOOT_PRINTF1("local_sbm1_nb_cwf_max %d \n", param_local.local_sbm1_nb_cwf_max)
293 BOOT_PRINTF1("local_sbm2_nb_cwf_max %d \n", param_local.local_sbm2_nb_cwf_max)
294 BOOT_PRINTF1("local_sbm2_nb_cwf_max %d \n", param_local.local_sbm2_nb_cwf_max)
294 BOOT_PRINTF1("nb_interrupt_f0_MAX = %d\n", param_local.local_nb_interrupt_f0_MAX)
295 BOOT_PRINTF1("nb_interrupt_f0_MAX = %d\n", param_local.local_nb_interrupt_f0_MAX)
295
296
296 // init sequence counters
297 // init sequence counters
297
298
298 for(i = 0; i<SEQ_CNT_NB_DEST_ID; i++)
299 for(i = 0; i<SEQ_CNT_NB_DEST_ID; i++)
299 {
300 {
300 sequenceCounters_TC_EXE[i] = 0x00;
301 sequenceCounters_TC_EXE[i] = 0x00;
301 sequenceCounters_TM_DUMP[i] = 0x00;
302 sequenceCounters_TM_DUMP[i] = 0x00;
302 }
303 }
303 sequenceCounters_SCIENCE_NORMAL_BURST = 0x00;
304 sequenceCounters_SCIENCE_NORMAL_BURST = 0x00;
304 sequenceCounters_SCIENCE_SBM1_SBM2 = 0x00;
305 sequenceCounters_SCIENCE_SBM1_SBM2 = 0x00;
305 sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << 8;
306 sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << 8;
306 }
307 }
307
308
308 void reset_local_time( void )
309 void reset_local_time( void )
309 {
310 {
310 time_management_regs->ctrl = time_management_regs->ctrl | 0x02; // [0010] software reset, coarse time = 0x80000000
311 time_management_regs->ctrl = time_management_regs->ctrl | 0x02; // [0010] software reset, coarse time = 0x80000000
311 }
312 }
312
313
313 void create_names( void ) // create all names for tasks and queues
314 void create_names( void ) // create all names for tasks and queues
314 {
315 {
315 /** This function creates all RTEMS names used in the software for tasks and queues.
316 /** This function creates all RTEMS names used in the software for tasks and queues.
316 *
317 *
317 * @return RTEMS directive status codes:
318 * @return RTEMS directive status codes:
318 * - RTEMS_SUCCESSFUL - successful completion
319 * - RTEMS_SUCCESSFUL - successful completion
319 *
320 *
320 */
321 */
321
322
322 // task names
323 // task names
323 Task_name[TASKID_RECV] = rtems_build_name( 'R', 'E', 'C', 'V' );
324 Task_name[TASKID_RECV] = rtems_build_name( 'R', 'E', 'C', 'V' );
324 Task_name[TASKID_ACTN] = rtems_build_name( 'A', 'C', 'T', 'N' );
325 Task_name[TASKID_ACTN] = rtems_build_name( 'A', 'C', 'T', 'N' );
325 Task_name[TASKID_SPIQ] = rtems_build_name( 'S', 'P', 'I', 'Q' );
326 Task_name[TASKID_SPIQ] = rtems_build_name( 'S', 'P', 'I', 'Q' );
326 Task_name[TASKID_LOAD] = rtems_build_name( 'L', 'O', 'A', 'D' );
327 Task_name[TASKID_LOAD] = rtems_build_name( 'L', 'O', 'A', 'D' );
327 Task_name[TASKID_AVF0] = rtems_build_name( 'A', 'V', 'F', '0' );
328 Task_name[TASKID_AVF0] = rtems_build_name( 'A', 'V', 'F', '0' );
328 Task_name[TASKID_SWBD] = rtems_build_name( 'S', 'W', 'B', 'D' );
329 Task_name[TASKID_SWBD] = rtems_build_name( 'S', 'W', 'B', 'D' );
329 Task_name[TASKID_WFRM] = rtems_build_name( 'W', 'F', 'R', 'M' );
330 Task_name[TASKID_WFRM] = rtems_build_name( 'W', 'F', 'R', 'M' );
330 Task_name[TASKID_DUMB] = rtems_build_name( 'D', 'U', 'M', 'B' );
331 Task_name[TASKID_DUMB] = rtems_build_name( 'D', 'U', 'M', 'B' );
331 Task_name[TASKID_HOUS] = rtems_build_name( 'H', 'O', 'U', 'S' );
332 Task_name[TASKID_HOUS] = rtems_build_name( 'H', 'O', 'U', 'S' );
332 Task_name[TASKID_PRC0] = rtems_build_name( 'P', 'R', 'C', '0' );
333 Task_name[TASKID_PRC0] = rtems_build_name( 'P', 'R', 'C', '0' );
333 Task_name[TASKID_CWF3] = rtems_build_name( 'C', 'W', 'F', '3' );
334 Task_name[TASKID_CWF3] = rtems_build_name( 'C', 'W', 'F', '3' );
334 Task_name[TASKID_CWF2] = rtems_build_name(<