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Mini LFR - Bitstream Generation » History » Version 16

Jean-Christophe Pellion, 06/12/2016 10:52 AM

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# Mini LFR - Bitstream Generation Procedure 
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## 1 Generates scripts files ##
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Clean the project directory, and run the makefile scripts command to generate all project's files.
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```bash
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# clean the project and re-generates the scripts
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$> make distclean scripts
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```
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The files MINI\_LFR\_top\_libero.prj should be created.
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## 2 Launch Libero IDE ##
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Open the project MINI\_LFR\_top\_libero.prj with Libero IDE v9.1.
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!["Libero IDE v9.1"](Capture1.PNG)
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### 2.1 Synthesis ###
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Synthesis tools should be configured to use **Synplify** version **2012-03A-SP1-2**.
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Launch the synthesis step (You must not add constraint file).
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In the synplify Pro windows, click on the Run button.
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The project status obtained should be :
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!["Synplify Project Status"](Capture2.PNG)
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> You must verfify the block RAM's usage. The expected value is 100.
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>
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> If it's around 60/70, LEON3 processor is not mapped. In this case, you must clean your project and restart the generation procedure.
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You can close Synplify and return to Libero.
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If the Sythesis step is green like that :
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You must activate the option `Detect new files on disk automatically` in the project settings.
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![](Capture3.PNG)
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![](Capture4.PNG)
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### 2.2 Place&Route ###
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Launch the Place&Route step. You must add the constraint files :
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  * `default.pdc` (Input/Output constraint)
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  * `MINI-LFR_PlaceAndRoute.sdc` (Timing constraint)
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![](Capture5.PNG)
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#### 2.2.1 Compile Step ####
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![](Capture6.PNG)
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Run the Compile step.
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#### 2.2.2 Layout Step ####
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![](Capture7.PNG)
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Run the Layout step.
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In the Layout options windows, select Advanced Layout Options :
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![](Capture8.PNG)
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And checked those options :
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![](Capture9.PNG)
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Click Ok and wait...
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![](Capture10.PNG)
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#### 2.2.3 Timing Analyser ####
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Launch theTiming Analyser.
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![](Capture11.PNG)
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#### 2.2.3.a SpaceWire Output ####
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You must verify the SpaceWire output timing for the Max and Min delay.
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![](Capture12.PNG)
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![](Capture19.PNG)
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The ouput skew is equal to Ouput\_SOut timing - Ouput\_DOut timing. This output skew must be positive.
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> In this exemple,
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> SPW\_NOM skew max = 13.907 - 15.882 = -1.975 ns
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> SPW\_NOM skew min = 6.367 - 7.317 = -0.950 ns
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> SPW\_RED skew max = 17.937 - 13.510 =  4.427 ns
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> SPW\_RED skew min = 8.304 - 6.175 =  2.129 ns
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> The SPW\_NOM interface must be modified. In ChipPlanner, we will move element in the SPW\_NOM path to have a positive skew in min and max delay.
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> ![](Capture13.PNG)
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> ![](Capture14.PNG)
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#### 2.2.3.b SpaceWire Input ####
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You must also verify the SpaceWire input timing. For that, you must add a new set for SPW_INPUT:
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![](Capture15.PNG)
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and configure it like that :
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 you
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![](Capture16.PNG)
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You obtain those timing for min and max delay.
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![](Capture17.PNG)
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![](Capture18.PNG)
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You must also add a new set for the FF setup time :
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![](Capture20.PNG)
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![](Capture21.PNG)
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In resume, for the input SPW_NOM interface :
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<table border=1 width=40% align=center>
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    	<thead>
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    		<tr>
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			<th colspan=2> Signal Type </th>		<th> max delay</th>	<th>min delay</th>
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    		</tr>
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    	</thead>
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    	<thead>
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    		<tr>
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			<th colspan=4 align="center" bgcolor="#C0C0C0"> SPW_NOM_IN </th>
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    		</tr>
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    	</thead>
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    	<tbody>
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        	<tr>	<td rowspan=4>r_FF</td> 	<td>Strobe to CLK</td>	<td>7.230 ns</td>	<td>3.497 ns</td>	</tr>
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		<tr>					<td>Data   to CLK</td>	<td>8.046 ns</td>	<td>3.807 ns</td>	</tr>
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		<tr>					<td>Data   to D  </td>	<td>1.700 ns</td>	<td>0.692 ns</td>	</tr>
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		<tr>					<td>D to Q  </td>	<td>0.888 ns</td>	<td>0.413 ns</td>	</tr>
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		<tr>	<td rowspan=4>nr_FF</td> 	<td>Strobe  to CLK</td>	<td>7.315 ns</td>	<td>3.543 ns</td>	</tr>
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		<tr>					<td>Data    to CLK</td>	<td>8.131 ns</td>	<td>3.853 ns</td>	</tr>
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		<tr>					<td>Data    to D  </td>	<td>1.767 ns</td>	<td>0.724 ns</td>	</tr>
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		<tr>					<td>D to Q  </td>	<td>0.888 ns</td>	<td>0.413 ns</td>	</tr>
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    	</tbody>
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    	<thead>
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    		<tr>
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			<th colspan=4 align="center" bgcolor="#C0C0C0"> SPW_RED_IN </th>
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    		</tr>
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    	</thead>
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    	<tbody>
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        	<tr>	<td rowspan=4>r_FF</td> 	<td>Strobe to CLK</td>	<td>11.601 ns</td>	<td>6.217 ns</td>	</tr>
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		<tr>					<td>Data   to CLK</td>	<td>12.845 ns</td>	<td>5.488 ns</td>	</tr>
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		<tr>					<td>Data   to D  </td>	<td>2.799 ns</td>	<td>1.246 ns</td>	</tr>
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		<tr>					<td>D to Q  </td>	<td>0.888 ns</td>	<td>0.413 ns</td>	</tr>
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		<tr>	<td rowspan=4>nr_FF</td> 	<td>Strobe  to CLK</td>	<td>11.628 ns</td>	<td>6.236 ns</td>	</tr>
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		<tr>					<td>Data    to CLK</td>	<td>12.872 ns</td>	<td>5.507 ns</td>	</tr>
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		<tr>					<td>Data    to D  </td>	<td>2.798 ns</td>	<td>1.246 ns</td>	</tr>
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		<tr>					<td>D to Q  </td>	<td>0.888 ns</td>	<td>0.413 ns</td>	</tr>
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    	</tbody>
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</table>
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The input skew is equal to : min(Time from strobe to CLK; Time from data to CLK) - Time Data to FF - FF Setup Time. This input skew must be positive.
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<table border=1 width=40% align=center>
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    	<thead>
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    		<tr>
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			<th> skew </th>			<th colspan=2>max delay</th>	<th colspan=2>min delay</th>
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    		</tr>
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    	</thead>
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    	<thead>
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    		<tr>
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			<th colspan=5 align="center" bgcolor="#C0C0C0"> SPW_NOM_IN </th>
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    		</tr>
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    	</thead>
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    	<tbody>
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        	<tr>	<td>skew r_FF</td> 	<td>4.642 ns</td>	<td bgcolor="#00FF00">OK</td>	<td>2.392 ns</td>	<td bgcolor="#00FF00">OK</td>	</tr>
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        	<tr>	<td>skew nr_FF</td> 	<td>4.660 ns</td>	<td bgcolor="#00FF00">OK</td>	<td>2.406 ns</td>	<td bgcolor="#00FF00">OK</td>	</tr>
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    	</tbody>
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    	<thead>
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    		<tr>
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			<th colspan=5 align="center" bgcolor="#C0C0C0"> SPW_RED_IN </th>
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    		</tr>
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    	</thead>
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    	<tbody>
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        	<tr>	<td>skew r_FF</td> 	<td>7.914 ns</td>	<td bgcolor="#00FF00">OK</td>	<td>3.829 ns</td>	<td bgcolor="#00FF00">OK</td>	</tr>
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        	<tr>	<td>skew nr_FF</td> 	<td>7.942 ns</td>	<td bgcolor="#00FF00">OK</td>	<td>3.848 ns</td>	<td bgcolor="#00FF00">OK</td>	</tr>
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    	</tbody>
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</table>
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In our case, all SPW input skew are positive.
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If MIN or MAX skew delay are not positive, you must launch the ChipPlanner tool to move r_FF and nr_FF closest to the CLK source and move XOR gate far away from input pads (SIN, DIN), nrFF:D and r_FF:D.
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You can close the Timing Analyser.
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#### 2.2.4 Chip Planner ####
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Launch ChipPlanner to move element in the netlist and try to fit the timing requirements (skew delay for the SPW\_NOM Output interface).
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![](Capture22.PNG)
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In our case, we want to increase  SPW\_NOM\  output skew. For that, we must increase Ouput\_SOut timing and reduce the Ouput\_DOut timing.
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To reduce the output dout delay, we will select the last FF before the SPW\_NOM\_OUTPUT :
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![](Capture23.PNG)
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and move closest to the ouput PAD :
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![](Capture24.PNG)
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To increase the output SOut delay, we will select the last FF before the SPW\_NOM\_OUTPUT :
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![](Capture25.PNG)
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and move far away from the ouput PAD :
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![](Capture26.PNG)
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Now, you can clicked on `Commit and Check` button and close ChipPlanner.
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You must relaunch the Layout step with those selected options :
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![](Capture27.PNG)
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And finally, checked the timing update with the Timing Analyser.
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### 2.2 Bitstream generation ###
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Click on the Programming File tool.
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![](Capture28.PNG)
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It's done !
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