Mini LFR - Bitstream Generation Procedure

1 Generates scripts files

Clean the project directory, and run the makefile scripts command to generate all project's files.

# clean the project and re-generates the scripts
$> make distclean scripts

The files MINI_LFR_top_libero.prj should be created.

2 Launch Libero IDE

Open the project MINI_LFR_top_libero.prj with Libero IDE v9.1.
"Libero IDE v9.1"

2.1 Synthesis

Synthesis tools should be configured to use Synplify version 2012-03A-SP1-2.

Launch the synthesis step (You must not add constraint file).
In the synplify Pro windows, click on the Run button.

The project status obtained should be :

"Synplify Project Status"

You must verfify the block RAM's usage. The expected value is 100.

If it's around 60/70, LEON3 processor is not mapped. In this case, you must clean your project and restart the generation procedure.

You can close Synplify and return to Libero.

If the Sythesis step is green like that :

You must activate the option Detect new files on disk automatically in the project settings.

2.2 Place&Route

Launch the Place&Route step. You must add the constraint files :

  • default.pdc (Input/Output constraint)
  • MINI-LFR_PlaceAndRoute.sdc (Timing constraint)

2.2.1 Compile Step

Run the Compile step.

2.2.2 Layout Step

Run the Layout step.

In the Layout options windows, select Advanced Layout Options :

And checked those options :

Click Ok and wait...

2.2.3 Timing Analyser

Launch theTiming Analyser.

2.2.3.a SpaceWire Output

You must verify the SpaceWire output timing for the Max and Min delay.

The ouput skew is equal to Ouput_SOut timing - Ouput_DOut timing. This output skew must be positive.

In this exemple,

SPW_NOM skew max = 13.907 - 15.882 = -1.975 ns

SPW_NOM skew min = 6.367 - 7.317 = -0.950 ns

SPW_RED skew max = 17.937 - 13.510 = 4.427 ns

SPW_RED skew min = 8.304 - 6.175 = 2.129 ns

The SPW_NOM interface must be modified. In ChipPlanner, we will move element in the SPW_NOM path to have a positive skew in min and max delay.

2.2.3.b SpaceWire Input

You must also verify the SpaceWire input timing. For that, you must add a new set for SPW_INPUT:

and configure it like that :

You obtain those timing for min and max delay.

You must also add a new set for the FF setup time :

In resume, for the input SPW_NOM interface :

Signal Type max delay min delay
r_FF Strobe to CLK 7.230 ns 3.497 ns
Data to CLK 8.046 ns 3.807 ns
Data to D 1.700 ns 0.692 ns
D to Q 0.888 ns 0.413 ns
nr_FF Strobe to CLK 7.315 ns 3.543 ns
Data to CLK 8.131 ns 3.853 ns
Data to D 1.767 ns 0.724 ns
D to Q 0.888 ns 0.413 ns
r_FF Strobe to CLK 11.601 ns 6.217 ns
Data to CLK 12.845 ns 5.488 ns
Data to D 2.799 ns 1.246 ns
D to Q 0.888 ns 0.413 ns
nr_FF Strobe to CLK 11.628 ns 6.236 ns
Data to CLK 12.872 ns 5.507 ns
Data to D 2.798 ns 1.246 ns
D to Q 0.888 ns 0.413 ns

The input skew is equal to : min(Time from strobe to CLK; Time from data to CLK) - Time Data to FF - FF Setup Time. This input skew must be positive.

skew max delay min delay
skew r_FF 4.642 ns OK 2.392 ns OK
skew nr_FF 4.660 ns OK 2.406 ns OK
skew r_FF 7.914 ns OK 3.829 ns OK
skew nr_FF 7.942 ns OK 3.848 ns OK

In our case, all SPW input skew are positive.
If MIN or MAX skew delay are not positive, you must launch the ChipPlanner tool to move r_FF and nr_FF closest to the CLK source and move XOR gate far away from input pads (SIN, DIN), nrFF:D and r_FF:D.

You can close the Timing Analyser.

2.2.4 Chip Planner

Launch ChipPlanner to move element in the netlist and try to fit the timing requirements (skew delay for the SPW_NOM Output interface).

In our case, we want to increase SPW_NOM\ output skew. For that, we must increase Ouput_SOut timing and reduce the Ouput_DOut timing.

To reduce the output dout delay, we will select the last FF before the SPW_NOM_OUTPUT :

and move closest to the ouput PAD :

To increase the output SOut delay, we will select the last FF before the SPW_NOM_OUTPUT :

and move far away from the ouput PAD :

Now, you can clicked on Commit and Check button and close ChipPlanner.

You must relaunch the Layout step with those selected options :

And finally, checked the timing update with the Timing Analyser.

2.2 Bitstream generation

Click on the Programming File tool.

It's done !

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