Schematics » History » Version 2
Alexis Jeandet, 16/10/2014 09:36 PM
| 1 | 1 | Alexis Jeandet | h1. Schematics |
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| 3 | h2. Top level |
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| 5 | 2 | Alexis Jeandet | !{width: 80%}QM_SOLO_LFR-01.08-TOP.jpg(Top level)! |
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| 7 | h2. Power supply |
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| 8 | |||
| 9 | !{width: 80%}QM_SOLO_LFR-01.08-PWR.jpg(Top level)! |
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| 10 | |||
| 11 | h2. Input buffer |
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| 12 | |||
| 13 | !{width: 80%}QM_SOLO_LFR-01.08-BUFF.jpg(Top level)! |
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| 14 | |||
| 15 | !{width: 80%}QM_SOLO_LFR-01.08-AN.jpg(Top level)! |
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| 17 | |||
| 18 | h2. Bias fail multiplexers |
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| 19 | |||
| 20 | !{width: 80%}QM_SOLO_LFR-01.08-BFAIL.jpg(Top level)! |
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| 21 | |||
| 22 | h2. ADCs |
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| 23 | |||
| 24 | !{width: 80%}QM_SOLO_LFR-01.08-ADC.jpg(Top level)! |
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| 25 | |||
| 26 | h2. Search Coil callibration |
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| 27 | |||
| 28 | !{width: 80%}QM_SOLO_LFR-01.08-CAL.jpg(Top level)! |
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| 29 | |||
| 30 | h2. Housekeepings |
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| 31 | |||
| 32 | !{width: 80%}QM_SOLO_LFR-01.08-HK.jpg(Top level)! |
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| 33 | |||
| 34 | h2. FPGA |
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| 35 | |||
| 36 | !{width: 80%}QM_SOLO_LFR-01.08-FPGA.jpg(Top level)! |
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| 37 | |||
| 38 | h2. SRAM |
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| 39 | |||
| 40 | !{width: 80%}QM_SOLO_LFR-01.08-SRAM.jpg(Top level)! |
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| 41 | |||
| 42 | h2. Spacewire |
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| 43 | |||
| 44 | !{width: 80%}QM_SOLO_LFR-01.08-SPW.jpg(Top level)! |
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| 47 | h2. Changelog |
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| 49 | !{width: 80%}QM_SOLO_LFR-01.08-Changelog.jpg(Top level)! |