Leon3FT fault tolerance » History » Version 7
paul leroy, 25/01/2016 01:56 PM
| 1 | 5 | paul leroy | h1. Leon3/FT fault tolerance |
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| 2 | 3 | paul leroy | |
| 3 | The explanations hereafter are extracted from the Gaisler IP cores user's manual (grip.pdf). |
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| 4 | 5 | paul leroy | There are two aspects in the fault tolerance: register file protection and cache protection. Each aspect is managed using a specific register: |
| 5 | 3 | paul leroy | * Cache protection is managed with the CCR (Cache Control Register) located in ASI 2, offet 0x00 |
| 6 | * Register file protection is managed with the ASR16, Register protection control register |
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| 7 | 4 | paul leroy | |
| 8 | 1 | paul leroy | h2. Cache Control Register (ASI 2, offset 0x00) |
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| 10 | 6 | paul leroy | |
| 11 | 7 | paul leroy | |
| 12 | 1 | paul leroy | h2. Register protection control register (ASR16) |
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| 14 | ASR register 16 (%asr16) is used to control the IU/FPU register file SEU protection. It is possible to disable the SEU protection by setting the IDI/FDI bits, and to inject errors using the ITE/FTE bits. |
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| 15 | Corrected errors in the register file are counted, and available in ICNT and FCNT fields. The counters saturate at their maximum value (7), and should be reset by software after read-out. |
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| 16 | 7 | paul leroy | |
| 17 | * 31:30 FP FT ID - Defines which SEU protection is implemented in the FPU (see table 1123) |
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| 18 | * 29:27 FP RF error counter - Number of detected parity errors in the FP register file. |
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| 19 | * 26:18 Reserved for future implementations |
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| 20 | * 17 FPU RF Test Enable - Enables FPU register file test mode. Parity bits are xored with TB before written to the FPU register file. |
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| 21 | * 16 FP RF protection disable (FDI) - Disables FP RF parity protection when set. |
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| 22 | * 15:14 IU FT ID - Defines which SEU protection is implemented in the IU (see table 1123) |
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| 23 | * 13:11 IU RF error counter - Number of detected parity errors in the IU register file. |
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| 24 | * 10:3 RF Test bits (RFTB) - In test mode, these bits are xored with correct parity bits before written to the register file. |
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| 25 | * 2 DP ram select (DP) - Only applicable if the IU or FPU register files consists of two dual-port rams. |
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| 26 | * 1 IU RF Test Enable - Enables register file test mode. Parity bits are xored with TB before written to the register file. |
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| 27 | * 0 IU RF protection disable (IDI) - Disables IU RF parity protection when set. |
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| 28 | 4 | paul leroy | |
| 29 | 3 | paul leroy | *ASI = Address Space Identifier |
| 30 | *ASR = Ancillary State Register |