Leon3FT fault tolerance » History » Version 5
paul leroy, 25/01/2016 01:51 PM
| 1 | 5 | paul leroy | h1. Leon3/FT fault tolerance |
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| 2 | 3 | paul leroy | |
| 3 | The explanations hereafter are extracted from the Gaisler IP cores user's manual (grip.pdf). |
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| 4 | 5 | paul leroy | There are two aspects in the fault tolerance: register file protection and cache protection. Each aspect is managed using a specific register: |
| 5 | 3 | paul leroy | * Cache protection is managed with the CCR (Cache Control Register) located in ASI 2, offet 0x00 |
| 6 | * Register file protection is managed with the ASR16, Register protection control register |
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| 7 | 4 | paul leroy | |
| 8 | 1 | paul leroy | h2. Cache Control Register (ASI 2, offset 0x00) |
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| 10 | 5 | paul leroy | |
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| 12 | 1 | paul leroy | h2. Register protection control register (ASR16) |
| 13 | 5 | paul leroy | |
| 14 | ASR register 16 (%asr16) is used to control the IU/FPU register file SEU protection. It is possible to disable the SEU protection by setting the IDI/FDI bits, and to inject errors using the ITE/FTE bits. |
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| 15 | Corrected errors in the register file are counted, and available in ICNT and FCNT fields. The counters saturate at their maximum value (7), and should be reset by software after read-out. |
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| 16 | 4 | paul leroy | |
| 17 | 3 | paul leroy | *ASI = Address Space Identifier |
| 18 | *ASR = Ancillary State Register |