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/*------------------------------------------------------------------------------
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-- This file is a part of the libuc, microcontroler library
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-- Copyright (C) 2011, Alexis Jeandet
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@gmail.com
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-------------------------------------------------------------------------------*/
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#include <spi.h>
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#include <stm32f4xx_rcc.h>
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#include <stm32f4xx_gpio.h>
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#include <gpio.h>
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#define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
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#define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
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SPI_TypeDef* _spi_dev_table[3]={SPI1,SPI2,SPI3};
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spi_t spiopen(int count)
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{
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#define _INIT_DEV(_RCC_) \
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RCC_APB1PeriphClockCmd(_RCC_, ENABLE); \
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RCC_APB1PeriphResetCmd(_RCC_, ENABLE); \
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RCC_APB1PeriphResetCmd(_RCC_, DISABLE); \
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RCC_APB1PeriphClockCmd(_RCC_, ENABLE);
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switch(count)
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{
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case spi1:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
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return spi1;
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break;
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case spi2:
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_INIT_DEV(RCC_APB1Periph_SPI2);
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return spi2;
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break;
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case spi3:
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_INIT_DEV(RCC_APB1Periph_SPI3);
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return spi3;
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break;
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default:
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break;
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}
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return -1;
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}
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spi_t spiopenandconfig(int count, uint32_t cfg, uint32_t speed, uint32_t MOSIpin, uint32_t MISOpin, uint32_t SCKpin, uint32_t SCSpin)
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{
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spi_t dev = spiopen(count);
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if(dev!=-1)
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{
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spidisable(dev);
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spisetpins(dev,MOSIpin, MISOpin, SCKpin, SCSpin);
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spienable(dev);
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spisetconfig(dev,cfg,speed);
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}
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return dev;
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}
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int spiclose(spi_t spidev)
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{
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if((spidev<3)&&(spidev>=0))
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{
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switch(spidev)
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{
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case spi1:
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
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break;
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case spi2:
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
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break;
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case spi3:
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
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break;
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default:
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return -1;
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break;
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}
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return 1;
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}
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return -1;
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}
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int spisetpins(spi_t spidev,uint32_t MOSIpin,uint32_t MISOpin,uint32_t SCKpin,uint32_t SCSpin)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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gpio_t MISO,MOSI,SCK,SCS;
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uint8_t gpioAFspix = GPIO_AF_SPI1;
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switch(spidev)
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{
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case spi1:
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gpioAFspix = GPIO_AF_SPI1;
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break;
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case spi2:
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gpioAFspix = GPIO_AF_SPI2;
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break;
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case spi3:
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gpioAFspix = GPIO_AF_SPI3;
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break;
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default:
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break;
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}
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if(MISOpin!=-1)
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{
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MISO = gpioopen(MISOpin);
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MISO |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
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gpiosetconfig(&MISO);
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GPIO_PinAFConfig(GPIOGETPORT(MISO), (uint8_t)(MISO & 0xF), gpioAFspix);
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}
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if(MOSIpin!=-1)
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{
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MOSI = gpioopen(MOSIpin);
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MOSI |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
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gpiosetconfig(&MOSI);
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GPIO_PinAFConfig(GPIOGETPORT(MOSI), (uint8_t)(MOSI & 0xF), gpioAFspix);
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}
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if(SCKpin!=-1)
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{
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SCK = gpioopen(SCKpin);
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SCK |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
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gpiosetconfig(&SCK);
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GPIO_PinAFConfig(GPIOGETPORT(SCK), (uint8_t)(SCK & 0xF), gpioAFspix);
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}
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if(SCSpin!=-1)
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{
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SCS = gpioopen(SCSpin);
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SCS |= gpiohighspeed | gpioaf | gpiopushpulltype | gpionopulltype;
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gpiosetconfig(&SCS);
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GPIO_PinAFConfig(GPIOGETPORT(SCS), (uint8_t)(SCS & 0xF), gpioAFspix);
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_dev_->CR2 |= (1<<2);
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}
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else
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{
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_dev_->CR2 &= ~(1<<2);
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}
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return 1;
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}
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return -1;
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}
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int spienable(spi_t spidev)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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_dev_->CR1 |= (1<<6);
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return 1;
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}
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return -1;
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}
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int spidisable(spi_t spidev)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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_dev_->CR1 &= ~(1<<6);
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return 1;
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}
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return -1;
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}
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int spisetconfig(spi_t spidev, uint32_t config, uint32_t speed)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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_dev_->CR2 |= (1<<2);
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_dev_->CR1 |= (1<<2);
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spisetspeed(spidev,speed);
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spisetdatabits(spidev,config & SPIBITSMASK);
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spisetbitorder(spidev,config & SPIBITORDERMASK);
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spisetclkinhlevel(spidev,config & SPICLKINHLVLMASK);
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spisetclkphase(spidev,config & SPICLKPHASEMASK);
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return 0;
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}
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return 1;
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}
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int spisetspeed(spi_t spidev, uint32_t speed)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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uint32_t apbclock = 0x00;
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RCC_ClocksTypeDef RCC_ClocksStatus;
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RCC_GetClocksFreq(&RCC_ClocksStatus);
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if (_dev_ == SPI1)
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{
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apbclock = RCC_ClocksStatus.PCLK2_Frequency;
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}
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else
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{
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apbclock = RCC_ClocksStatus.PCLK1_Frequency;
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}
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int32_t speederror = 0x7FFFFFFF; //max error
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int32_t prev_speederror = 0x7FFFFFFF;
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int32_t realspeed = 0;
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unsigned char divider = 0;
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do
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{
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divider ++;
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prev_speederror = speederror;
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realspeed = apbclock>>(divider);
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speederror = realspeed - speed;
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if(speederror<0)speederror=-speederror;
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if(divider>8)break;
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}while(speederror<prev_speederror);
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speed = apbclock>>(divider-1);
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divider-=2;
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_dev_->CR1 &= 0xFFD7; // clear prescaler bits 3:5
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_dev_->CR1 |= ((0x7 & divider)<<3);
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return 1;
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}
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return -1;
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}
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int spisetdatabits(spi_t spidev,spibits_t bitscnt)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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int result = 0;
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switch(bitscnt)
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{
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case spi8bits:
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_dev_->CR1 &= ~(1<<11);
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result = 1;
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break;
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case spi16bits:
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_dev_->CR1 |= (1<<11);
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result = 1;
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break;
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default:
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result =-1;
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break;
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}
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return result;
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}
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return -1;
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}
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int spisetbitorder(spi_t spidev,spibitorder_t order)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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if(order==spimsbfirst)
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{
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_dev_->CR1 &= ~(1<<7);
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return 1;
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}
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else
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{
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if(order==spilsbfirst)
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{
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_dev_->CR1 |= (1<<7);
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return 1;
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}
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else return -1;
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}
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}
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return -1;
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}
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int spisetclkinhlevel(spi_t spidev,spiclkinhlvl_t level)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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if(level==spiclkinhlow)
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{
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_dev_->CR1 &= ~(1<<1);
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return 1;
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}
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else
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{
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if(level==spiclkinhhigh)
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{
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_dev_->CR1 |= (1<<1);
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return 1;
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}
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else return -1;
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}
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}
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return -1;
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}
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int spisetclkphase(spi_t spidev,spiclkphase_t phase)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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if(phase==spiclkfirstedge)
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{
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_dev_->CR1 &= ~1;
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return 1;
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}
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else
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{
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if(phase==spiclksecondedge)
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{
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_dev_->CR1 |= 1;
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return 1;
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}
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else return -1;
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}
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}
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return -1;
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}
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int spiputw(spi_t spidev,uint16_t data)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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_dev_->DR = data;
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while((_dev_->SR & (1<<7)) == (1<<7));
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return 1;
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}
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return -1;
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}
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uint16_t spigetw(spi_t spidev)
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{
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if((spidev<3)&&(spidev>=0))
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{
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SPI_TypeDef* _dev_ = _spi_dev_table[(int)spidev];
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while((_dev_->SR & (1<<7)) == (1<<7));
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_dev_->DR = 0xFFFF;
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while((_dev_->SR & (1<<0)) == 0);
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return _dev_->DR;
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}
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return -1;
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}
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int spiputs(spi_t spidev,char* s)
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{
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while (*s) spiputw(spidev,*s++);
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return 1;
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}
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int spigets(spi_t spidev,char* s)
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{
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do
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{
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(*s) = spigetw(spidev);
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}
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while(*s++);
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return 1;
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}
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int spiputnw(spi_t spidev,uint16_t* w,int n)
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{
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while(n!=0)
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{
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spiputw(spidev,*w++);
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n--;
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}
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return 1;
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}
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int spigetnw(spi_t spidev,uint16_t* w,int n)
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{
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while(n!=0)
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{
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*w++=spigetw(spidev);
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n--;
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}
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return 1;
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}
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int spiputnc(spi_t spidev,char* c,int n)
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{
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while(n!=0)
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{
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spiputw(spidev,*c++);
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n--;
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}
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return 1;
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}
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int spigetnc(spi_t spidev,char* c,int n)
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{
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while(n!=0)
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{
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*c++=spigetw(spidev);
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n--;
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}
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return 1;
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}
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int spiavailiabledata(spi_t spidev)
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{
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return 0;
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}
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