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/*-----------------------------------------------------------------------------
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* Copyright (C) 2010 ARM Limited. All rights reserved.
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*
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* $Date: 15. July 2011
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* $Revision: V1.0.10
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*
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* Project: CMSIS DSP Library
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* Title: arm_biquad_cascade_df1_init_q15.c
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*
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* Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function.
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*
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* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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*
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* Version 1.0.10 2011/7/15
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* Big Endian support added and Merged M0 and M3/M4 Source code.
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*
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* Version 1.0.3 2010/11/29
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* Re-organized the CMSIS folders and updated documentation.
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*
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* Version 1.0.2 2010/11/11
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* Documentation updated.
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*
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* Version 1.0.1 2010/10/05
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* Production release and review comments incorporated.
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*
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* Version 1.0.0 2010/09/20
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* Production release and review comments incorporated.
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*
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* Version 0.0.5 2010/04/26
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* incorporated review comments and updated with latest CMSIS layer
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*
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* Version 0.0.3 2010/03/10
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* Initial version
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* ---------------------------------------------------------------------------*/
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#include "arm_math.h"
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/**
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* @ingroup groupFilters
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*/
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/**
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* @addtogroup BiquadCascadeDF1
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* @{
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*/
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/**
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* @details
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*
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* @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
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* @param[in] numStages number of 2nd order stages in the filter.
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* @param[in] *pCoeffs points to the filter coefficients.
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* @param[in] *pState points to the state buffer.
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* @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format
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* @return none
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*
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* <b>Coefficient and State Ordering:</b>
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*
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* \par
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* The coefficients are stored in the array <code>pCoeffs</code> in the following order:
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* <pre>
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* {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
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* </pre>
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* where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
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* <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
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* and so on. The <code>pCoeffs</code> array contains a total of <code>6*numStages</code> values.
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* The zero coefficient between <code>b1</code> and <code>b2</code> facilities use of 16-bit SIMD instructions on the Cortex-M4.
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*
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* \par
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* The state variables are stored in the array <code>pState</code>.
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* Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
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* The state variables are arranged in the <code>pState</code> array as:
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* <pre>
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* {x[n-1], x[n-2], y[n-1], y[n-2]}
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* </pre>
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* The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
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* The state array has a total length of <code>4*numStages</code> values.
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* The state variables are updated after each block of data is processed; the coefficients are untouched.
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*/
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void arm_biquad_cascade_df1_init_q15(
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arm_biquad_casd_df1_inst_q15 * S,
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uint8_t numStages,
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q15_t * pCoeffs,
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q15_t * pState,
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int8_t postShift)
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{
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/* Assign filter stages */
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S->numStages = numStages;
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/* Assign postShift to be applied to the output */
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S->postShift = postShift;
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/* Assign coefficient pointer */
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S->pCoeffs = pCoeffs;
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/* Clear state buffer and size is always 4 * numStages */
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memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
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/* Assign state pointer */
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S->pState = pState;
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}
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/**
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* @} end of BiquadCascadeDF1 group
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*/
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