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/**
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******************************************************************************
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* @file stm32f4xx_pwr.c
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* @author MCD Application Team
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* @version V1.0.0RC1
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* @date 25-August-2011
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* @brief This file provides firmware functions to manage the following
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* functionalities of the Power Controller (PWR) peripheral:
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* - Backup Domain Access
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* - PVD configuration
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* - WakeUp pin configuration
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* - Backup Regulator configuration
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* - Performance Mode and FLASH Power Down configuration functions
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* - Low Power modes configuration
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* - Flags management
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*
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_pwr.h"
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#include "stm32f4xx_rcc.h"
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup PWR
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* @brief PWR driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* --------- PWR registers bit address in the alias region ---------- */
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#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
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/* --- CR Register ---*/
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/* Alias word address of DBP bit */
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#define CR_OFFSET (PWR_OFFSET + 0x00)
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#define DBP_BitNumber 0x08
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#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
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/* Alias word address of PVDE bit */
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#define PVDE_BitNumber 0x04
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#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
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/* Alias word address of FPDS bit */
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#define FPDS_BitNumber 0x09
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#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
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/* Alias word address of PMODE bit */
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#define PMODE_BitNumber 0x0E
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#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
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/* --- CSR Register ---*/
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/* Alias word address of EWUP bit */
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#define CSR_OFFSET (PWR_OFFSET + 0x04)
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#define EWUP_BitNumber 0x08
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#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
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/* Alias word address of BRE bit */
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#define BRE_BitNumber 0x09
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#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
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/* ------------------ PWR registers bit mask ------------------------ */
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/* CR register bit mask */
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#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
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#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup PWR_Private_Functions
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* @{
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*/
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/** @defgroup PWR_Group1 Backup Domain Access function
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* @brief Backup Domain Access function
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*
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@verbatim
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===============================================================================
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Backup Domain Access function
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===============================================================================
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After reset, the backup domain (RTC registers, RTC backup data
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registers and backup SRAM) is protected against possible unwanted
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write accesses.
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To enable access to the RTC Domain and RTC registers, proceed as follows:
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- Enable the Power Controller (PWR) APB1 interface clock using the
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RCC_APB1PeriphClockCmd() function.
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- Enable access to RTC domain using the PWR_BackupAccessCmd() function.
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitializes the PWR peripheral registers to their default reset values.
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* @param None
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* @retval None
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*/
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void PWR_DeInit(void)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
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}
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/**
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* @brief Enables or disables access to the backup domain (RTC registers, RTC
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* backup data registers and backup SRAM).
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* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
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* Backup Domain Access should be kept enabled.
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* @param NewState: new state of the access to the backup domain.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_BackupAccessCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
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}
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/**
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* @}
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*/
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/** @defgroup PWR_Group2 PVD configuration functions
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* @brief PVD configuration functions
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*
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@verbatim
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===============================================================================
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PVD configuration functions
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===============================================================================
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- The PVD is used to monitor the VDD power supply by comparing it to a threshold
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selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
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- A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
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PVD threshold. This event is internally connected to the EXTI line16
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and can generate an interrupt if enabled through the EXTI registers.
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- The PVD is stopped in Standby mode.
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@endverbatim
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* @{
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*/
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/**
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* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
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* @param PWR_PVDLevel: specifies the PVD detection level
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* This parameter can be one of the following values:
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* @arg PWR_PVDLevel_0: PVD detection level set to 2.0V
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* @arg PWR_PVDLevel_1: PVD detection level set to 2.2V
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* @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
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* @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
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* @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
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* @arg PWR_PVDLevel_5: PVD detection level set to 2.8V
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* @arg PWR_PVDLevel_6: PVD detection level set to 2.9V
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* @arg PWR_PVDLevel_7: PVD detection level set to 3.0V
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* @note Refer to the electrical characteristics of you device datasheet for more details.
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* @retval None
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*/
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void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
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tmpreg = PWR->CR;
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/* Clear PLS[7:5] bits */
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tmpreg &= CR_PLS_MASK;
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/* Set PLS[7:5] bits according to PWR_PVDLevel value */
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tmpreg |= PWR_PVDLevel;
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/* Store the new value */
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PWR->CR = tmpreg;
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}
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/**
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* @brief Enables or disables the Power Voltage Detector(PVD).
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* @param NewState: new state of the PVD.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_PVDCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
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}
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/**
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* @}
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*/
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/** @defgroup PWR_Group3 WakeUp pin configuration functions
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* @brief WakeUp pin configuration functions
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*
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@verbatim
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===============================================================================
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WakeUp pin configuration functions
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===============================================================================
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- WakeUp pin is used to wakeup the system from Standby mode. This pin is
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forced in input pull down configuration and is active on rising edges.
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- There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
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@endverbatim
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* @{
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*/
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/**
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* @brief Enables or disables the WakeUp Pin functionality.
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* @param NewState: new state of the WakeUp Pin functionality.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_WakeUpPinCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
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}
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/**
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* @}
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*/
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/** @defgroup PWR_Group4 Backup Regulator configuration functions
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* @brief Backup Regulator configuration functions
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*
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@verbatim
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===============================================================================
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Backup Regulator configuration functions
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===============================================================================
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- The backup domain includes 4 Kbytes of backup SRAM accessible only from the
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CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained
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even in Standby or VBAT mode when the low power backup regulator is enabled.
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It can be considered as an internal EEPROM when VBAT is always present.
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You can use the PWR_BackupRegulatorCmd() function to enable the low power
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backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is
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ready or not.
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- When the backup domain is supplied by VDD (analog switch connected to VDD)
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the backup SRAM is powered from VDD which replaces the VBAT power supply to
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save battery life.
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- The backup SRAM is not mass erased by an tamper event. It is read protected
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to prevent confidential data, such as cryptographic private key, from being
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accessed. The backup SRAM can be erased only through the Flash interface when
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a protection level change from level 1 to level 0 is requested.
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Refer to the description of Read protection (RDP) in the Flash programming manual.
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@endverbatim
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* @{
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*/
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/**
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* @brief Enables or disables the Backup Regulator.
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* @param NewState: new state of the Backup Regulator.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_BackupRegulatorCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
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}
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/**
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* @}
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*/
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/** @defgroup PWR_Group5 Performance Mode and FLASH Power Down configuration functions
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* @brief Performance Mode and FLASH Power Down configuration functions
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*
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@verbatim
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===============================================================================
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Performance Mode and FLASH Power Down configuration functions
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===============================================================================
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- By setting the PMODE bit in the PWR_CR register by using the PWR_HighPerformanceModeCmd()
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function, the high performance mode is selected and the high voltage regulator
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minimum value should be around 1.2V.
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When reset, the low performance mode is selected and the low voltage regulator
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minimum value should be around 1.08V.
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- By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
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function, the Flash memory also enters power down mode when the device enters
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Stop mode. When the Flash memory is in power down mode, an additional startup
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delay is incurred when waking up from Stop mode.
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@endverbatim
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* @{
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*/
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/**
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* @brief Enables or disables the high performance mode.
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* @param NewState: new state of the performance mode.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_HighPerformanceModeCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_PMODE_BB = (uint32_t)NewState;
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}
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/**
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* @brief Enables or disables the Flash Power Down in STOP mode.
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* @param NewState: new state of the Flash power mode.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_FlashPowerDownCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
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}
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/**
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* @}
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*/
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/** @defgroup PWR_Group6 Low Power modes configuration functions
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* @brief Low Power modes configuration functions
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*
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@verbatim
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===============================================================================
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Low Power modes configuration functions
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===============================================================================
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The devices feature 3 low-power modes:
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- Sleep mode: Cortex-M4 core stopped, peripherals kept running.
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- Stop mode: all clocks are stopped, regulator running, regulator in low power mode
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- Standby mode: 1.2V domain powered off.
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Sleep mode
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===========
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- Entry:
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- The Sleep mode is entered by using the __WFI() or __WFE() functions.
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- Exit:
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- Any peripheral interrupt acknowledged by the nested vectored interrupt
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controller (NVIC) can wake up the device from Sleep mode.
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Stop mode
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==========
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In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
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and the HSE RC oscillators are disabled. Internal SRAM and register contents
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are preserved.
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The voltage regulator can be configured either in normal or low-power mode.
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To minimize the consumption In Stop mode, FLASH can be powered off before
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entering the Stop mode. It can be switched on again by software after exiting
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the Stop mode using the PWR_FlashPowerDownCmd() function.
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- Entry:
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- The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
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function with regulator in LowPower or with Regulator ON.
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- Exit:
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- Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
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Standby mode
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============
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The Standby mode allows to achieve the lowest power consumption. It is based
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on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
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The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
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the HSE oscillator are also switched off. SRAM and register contents are lost
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except for the RTC registers, RTC backup registers, backup SRAM and Standby
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circuitry.
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The voltage regulator is OFF.
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- Entry:
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- The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
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- Exit:
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- WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
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tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
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Auto-wakeup (AWU) from low-power mode
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=====================================
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The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
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Wakeup event, a tamper event, a time-stamp event, or a comparator event,
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without depending on an external interrupt (Auto-wakeup mode).
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- RTC auto-wakeup (AWU) from the Stop mode
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----------------------------------------
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- To wake up from the Stop mode with an RTC alarm event, it is necessary to:
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- Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
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or Event modes) using the EXTI_Init() function.
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- Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
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- Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
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and RTC_AlarmCmd() functions.
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- To wake up from the Stop mode with an RTC Tamper or time stamp event, it
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is necessary to:
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- Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
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or Event modes) using the EXTI_Init() function.
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|
|
- Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
|
|
function
|
|
|
- Configure the RTC to detect the tamper or time stamp event using the
|
|
|
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
|
|
functions.
|
|
|
- To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
|
|
|
- Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
|
|
|
or Event modes) using the EXTI_Init() function.
|
|
|
- Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
|
|
|
- Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
|
|
|
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
|
|
|
|
|
|
- RTC auto-wakeup (AWU) from the Standby mode
|
|
|
-------------------------------------------
|
|
|
- To wake up from the Standby mode with an RTC alarm event, it is necessary to:
|
|
|
- Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
|
|
|
- Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
|
|
and RTC_AlarmCmd() functions.
|
|
|
- To wake up from the Standby mode with an RTC Tamper or time stamp event, it
|
|
|
is necessary to:
|
|
|
- Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
|
|
function
|
|
|
- Configure the RTC to detect the tamper or time stamp event using the
|
|
|
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
|
|
functions.
|
|
|
- To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
|
|
|
- Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
|
|
|
- Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
|
|
|
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
|
|
|
|
|
|
@endverbatim
|
|
|
* @{
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @brief Enters STOP mode.
|
|
|
*
|
|
|
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
|
|
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
|
|
* the HSI RC oscillator is selected as system clock.
|
|
|
* @note When the voltage regulator operates in low power mode, an additional
|
|
|
* startup delay is incurred when waking up from Stop mode.
|
|
|
* By keeping the internal regulator ON during Stop mode, the consumption
|
|
|
* is higher although the startup time is reduced.
|
|
|
*
|
|
|
* @param PWR_Regulator: specifies the regulator state in STOP mode.
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg PWR_Regulator_ON: STOP mode with regulator ON
|
|
|
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
|
|
|
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
|
|
|
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
|
|
|
* @retval None
|
|
|
*/
|
|
|
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
|
|
{
|
|
|
uint32_t tmpreg = 0;
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
|
|
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
|
|
|
|
|
/* Select the regulator state in STOP mode ---------------------------------*/
|
|
|
tmpreg = PWR->CR;
|
|
|
/* Clear PDDS and LPDSR bits */
|
|
|
tmpreg &= CR_DS_MASK;
|
|
|
|
|
|
/* Set LPDSR bit according to PWR_Regulator value */
|
|
|
tmpreg |= PWR_Regulator;
|
|
|
|
|
|
/* Store the new value */
|
|
|
PWR->CR = tmpreg;
|
|
|
|
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
|
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
|
|
|
|
|
/* Select STOP mode entry --------------------------------------------------*/
|
|
|
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
|
|
{
|
|
|
/* Request Wait For Interrupt */
|
|
|
__WFI();
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Request Wait For Event */
|
|
|
__WFE();
|
|
|
}
|
|
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
|
|
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Enters STANDBY mode.
|
|
|
* @note In Standby mode, all I/O pins are high impedance except for:
|
|
|
* - Reset pad (still available)
|
|
|
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
|
|
|
* Alarm out, or RTC clock calibration out.
|
|
|
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
|
|
|
* - WKUP pin 1 (PA0) if enabled.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void PWR_EnterSTANDBYMode(void)
|
|
|
{
|
|
|
/* Clear Wakeup flag */
|
|
|
PWR->CR |= PWR_CR_CWUF;
|
|
|
|
|
|
/* Select STANDBY mode */
|
|
|
PWR->CR |= PWR_CR_PDDS;
|
|
|
|
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
|
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
|
|
|
|
|
/* This option is used to ensure that store operations are completed */
|
|
|
#if defined ( __CC_ARM )
|
|
|
__force_stores();
|
|
|
#endif
|
|
|
/* Request Wait For Interrupt */
|
|
|
__WFI();
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/** @defgroup PWR_Group7 Flags management functions
|
|
|
* @brief Flags management functions
|
|
|
*
|
|
|
@verbatim
|
|
|
===============================================================================
|
|
|
Flags management functions
|
|
|
===============================================================================
|
|
|
|
|
|
@endverbatim
|
|
|
* @{
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @brief Checks whether the specified PWR flag is set or not.
|
|
|
* @param PWR_FLAG: specifies the flag to check.
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
|
|
* was received from the WKUP pin or from the RTC alarm (Alarm A
|
|
|
* or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
|
|
|
* An additional wakeup event is detected if the WKUP pin is enabled
|
|
|
* (by setting the EWUP bit) when the WKUP pin level is already high.
|
|
|
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
|
|
* resumed from StandBy mode.
|
|
|
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
|
|
* by the PWR_PVDCmd() function. The PVD is stopped by Standby mode
|
|
|
* For this reason, this bit is equal to 0 after Standby or reset
|
|
|
* until the PVDE bit is set.
|
|
|
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
|
|
|
* when the device wakes up from Standby mode or by a system reset
|
|
|
* or power reset.
|
|
|
* @arg PWR_FLAG_REGRDY: Main regulator ready flag.
|
|
|
* @retval The new state of PWR_FLAG (SET or RESET).
|
|
|
*/
|
|
|
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
|
|
{
|
|
|
FlagStatus bitstatus = RESET;
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
|
|
|
|
|
|
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
|
|
{
|
|
|
bitstatus = SET;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
bitstatus = RESET;
|
|
|
}
|
|
|
/* Return the flag status */
|
|
|
return bitstatus;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Clears the PWR's pending flags.
|
|
|
* @param PWR_FLAG: specifies the flag to clear.
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg PWR_FLAG_WU: Wake Up flag
|
|
|
* @arg PWR_FLAG_SB: StandBy flag
|
|
|
* @retval None
|
|
|
*/
|
|
|
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
|
|
|
|
|
|
PWR->CR |= PWR_FLAG << 2;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
|
|
|
