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/*------------------------------------------------------------------------------
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-- This file is a part of the libuc, microcontroler library
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-- Copyright (C) 2011, Alexis Jeandet
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@gmail.com
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-------------------------------------------------------------------------------*/
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#include <core.h>
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#include <stm32f4xx_rcc.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <core_cm4.h>
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#include <gpio.h>
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extern uint32_t OSC0;
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extern uint32_t INTOSC;
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extern uint32_t RTCOSC;
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volatile uint32_t tickCounter=0;
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void SysTick_Handler(void)
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{
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tickCounter+=1;
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if((tickCounter&0xFFF)==0x800)
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gpiosetval(PC15,!gpiogetval(PC15));
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}
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void delay_us(uint32_t value)
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{
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extern uint32_t currentCpuFreq;
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if(value)
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{
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uint32_t tickperus=currentCpuFreq/(1000*10);
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uint32_t tickCounterSnap = SysTick->VAL+((value%100)*tickperus);
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uint32_t targetVal=tickCounterSnap +(value/100);
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if(targetVal < tickCounterSnap)
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{
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while(tickCounter > targetVal);
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}
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while((tickCounter < targetVal) | (SysTick->VAL<tickCounterSnap));
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}
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}
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void delay_100us(uint32_t value)
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{
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if(value)
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{
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uint32_t tickCounterSnap = tickCounter;
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uint32_t SysTickSnap = SysTick->VAL;
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uint32_t targetVal=tickCounterSnap +(value);
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if(targetVal < tickCounterSnap)
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{
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while(tickCounter > targetVal);
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}
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while((tickCounter < targetVal) | (SysTick->VAL<SysTickSnap));
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}
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}
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uint32_t getAPB1Freq()
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{
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RCC_ClocksTypeDef RCC_ClocksStatus;
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RCC_GetClocksFreq(&RCC_ClocksStatus);
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return RCC_ClocksStatus.PCLK1_Frequency;
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}
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uint32_t getAPB2Freq()
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{
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RCC_ClocksTypeDef RCC_ClocksStatus;
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RCC_GetClocksFreq(&RCC_ClocksStatus);
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return RCC_ClocksStatus.PCLK2_Frequency;
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}
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uint32_t getCpuFreq()
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{
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uint32_t cpufreq = OSC0;
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uint32_t PLLN,PLLM,PLLP;
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if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk
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{
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uint32_t pllinput=INTOSC;
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if((RCC->PLLCFGR & (1<<22)) == (1<<22))
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{
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pllinput=OSC0;
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}
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PLLN = (RCC->PLLCFGR>>6) & 0x1FF;
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PLLM = RCC->PLLCFGR & 0x3F;
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PLLP = 1<<(((RCC->PLLCFGR>>16) & 3 )+1);
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cpufreq = (pllinput * PLLN )/(PLLM*PLLP);
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}
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else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk
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{
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cpufreq=INTOSC;
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}
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if((RCC->CFGR & (1<<7))==1<<7)
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{
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return cpufreq>>((RCC->CFGR & (7<<4))>>4);
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}
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return cpufreq;
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}
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void reset_AHB1()
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{
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RCC->AHB1RSTR = -1;
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RCC->AHB1RSTR = 0;
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}
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void reset_AHB2()
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{
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RCC->AHB2RSTR = -1;
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RCC->AHB2RSTR = 0;
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}
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void reset_APB1()
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{
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RCC->APB1RSTR = -1;
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RCC->APB1RSTR = 0;
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}
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void reset_APB2()
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{
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RCC->APB2RSTR = -1;
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RCC->APB2RSTR = 0;
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}
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/*
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| 2.7->3.6V
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-------------------------
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0WS | 0<HCLK<=30
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1WS | 30<HCLK<=60
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2WS | 60<HCLK<=90
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3WS | 90<HCLK<=120
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4WS | 120<HCLK<=150
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5WS | 150<HCLK<=168
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f(VCO clock) = f(PLL clock input) × (PLLN / PLLM) [1]
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64MHz <= f(VCO clock) <= 432MHz [2]
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f(VCO clock input) must be between 1MHz and 2MHz and as close to 2MHz as possible!! [3]
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f(PLL general clock output) = f(VCO clock) / PLLP [4]
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CPU<168MHz AHB1<168MHz AHB2<168MHz APB1<42MHz APB2<84MHz [5]
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! 63<=PLLN<=432 [6]
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! 2<=PLLM<=63 [7]
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! PLLP=2,4,6,8 [8]
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4<=PLLM*PLLP<=504
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F= f(PLL clock input) * A/B with
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63<=A<=432
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4<=B<=504
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*/
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int optimizePLLcfg(uint32_t freq, uint32_t srcfreq,uint32_t PLLM,uint32_t* PLLP, uint32_t* PLLN,uint8_t* AHBPRindx)
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{
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uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512};
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uint32_t AHBPR=0,AHBPR_r=0,PLLN_r=0,PLLP_r=0;
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uint32_t Fplli=0;
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int32_t f_error=100000000;
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int32_t f_errornw=100000000;
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Fplli = srcfreq / PLLM;
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//not efficient but should find the best parameters
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for((*AHBPRindx)=0;(*AHBPRindx)<9;(*AHBPRindx)++) //lowest priority
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{
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AHBPR = AHBPRtbl[(*AHBPRindx)];
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for(*PLLP=2;*PLLP<9;*PLLP+=2)
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{
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*PLLN = (freq*(*PLLP)*AHBPR)/Fplli;
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if(((*PLLN)>62) && ((*PLLN)<433) && ((Fplli * (*PLLN)) < 433000000))
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{
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f_errornw = abs((int32_t)((int32_t)((Fplli*(*PLLN))/((*PLLP)*AHBPR))-freq));
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if( ( (f_error)>(f_errornw) ) || ( (*AHBPRindx==0)&&(*PLLP==2)&&(*PLLN==63) ) )
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{
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f_error=f_errornw;
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PLLN_r = *PLLN;
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PLLP_r = *PLLP;
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AHBPR_r=*AHBPRindx;
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if(f_error==0)
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{
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*PLLN = PLLN_r;
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*PLLP = PLLP_r;
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*AHBPRindx = AHBPR_r;
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return 1;
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}
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}
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}
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}
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}
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*PLLN = PLLN_r;
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*PLLP = PLLP_r;
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*AHBPRindx = AHBPR_r;
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return 1;
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}
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int setPll(uint32_t freq)
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{
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extern uint32_t OSC0;
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extern uint32_t INTOSC;
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uint32_t srcfreq = INTOSC;
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uint8_t AHBPRindx;
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uint32_t AHBPRtbl[9]={1,2,4,8,16,64,128,256,512};
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uint32_t PLLN=0,PLLM=0,PLLP=0,AHBPR=0;
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uint32_t Fplli=0;
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if((RCC->PLLCFGR & (1<<22))==(1<<22))
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{
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srcfreq = OSC0;
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}
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PLLM = srcfreq / 1500000; // [3]
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Fplli = srcfreq / PLLM;
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optimizePLLcfg(freq,srcfreq,PLLM,&PLLP,&PLLN,&AHBPRindx);
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srcfreq = (Fplli*PLLN)/(PLLP*AHBPRtbl[AHBPRindx]); //Put real clk freq in srcfreq for return value
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//now switch to HSIs
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if((RCC->CR & 1)==0)RCC->CR |= 1; //turn ON HSI
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while((RCC->CR & 2)!=2); //wait for HSI Ready
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= RCC_CFGR_SW_HSI; //set HSI as main clk
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_HSI);
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RCC->CR &= ~(1<<24); //Turn OFF PLL
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RCC->PLLCFGR &= ~0x37FFF; //clear PLLP PLLM PLLN
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RCC->PLLCFGR |= PLLM + (PLLN<<6) + (((PLLP>>1) -1)<<16);
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RCC->CR |= RCC_CR_PLLON; //Turn ON PLL
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while((RCC->CR & (1<<25))!=(1<<25)); //wait for PLL Ready
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if(AHBPRindx!=0)AHBPRindx|=0x8;
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RCC->CFGR &= ~(0xF<<4);
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RCC->CFGR |= (uint32_t)(AHBPRindx<<4);
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AHBPR=0;
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while((srcfreq>>AHBPR)>42000000)AHBPR++; //[5] //Thune APB1 prescaler to keep APB1 CLK below 42MHz
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if(AHBPR!=0)
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{
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AHBPR-=1;
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AHBPR|=0x4;
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}
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RCC->CFGR &= ~(0x7<<10);
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RCC->CFGR |= (uint32_t)(AHBPR<<10);
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AHBPR=0;
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while((srcfreq>>AHBPR)>84000000)AHBPR++; //[5] //Thune APB2 prescaler to keep APB2 CLK below 42MHz
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if(AHBPR!=0)
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{
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AHBPR-=1;
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AHBPR|=0x4;
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}
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RCC->CFGR &= ~(0x7<<13);
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RCC->CFGR |= (uint32_t)(AHBPR<<13);
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FLASH->ACR |= FLASH_ACR_LATENCY_7WS;
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));//Switch to PLL as main clk source
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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/* Wait untill the main PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
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if(srcfreq>150000000)
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{
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FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_5WS;
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}
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if((srcfreq<150000000) && (srcfreq>=120000000))
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{
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FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_4WS;
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}
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if((srcfreq<120000000) && (srcfreq>=90000000))
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{
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FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_3WS;
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}
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if((srcfreq<90000000) && (srcfreq>=60000000))
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{
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FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_2WS;
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}
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if((srcfreq<60000000) && (srcfreq>=30000000))
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{
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FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_1WS;
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}
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if(srcfreq<30000000)
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{
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FLASH->ACR &= (~7)|FLASH_ACR_LATENCY_0WS;
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}
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return srcfreq;
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}
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void configureSysTick()
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{
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extern uint32_t currentCpuFreq;
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uint32_t us=currentCpuFreq/(1000*10);
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SysTick_Config(us);
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}
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int setCpuFreq(uint32_t freq)
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{
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extern uint32_t OSC0;
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extern uint32_t INTOSC;
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uint8_t i=0;
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uint32_t curentFeq = getCpuFreq();
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if(curentFeq==freq)return curentFeq;
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if((freq>2000000) && (freq<=250000000)) //be carefull with 250MHz!!!
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{
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if((RCC->CFGR & 0xC) == 8) //PLL used as sys clk
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{
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return setPll(freq);
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}
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else if((RCC->CFGR & 0xC) == 0) //HSI used as sys clk
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{
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if((INTOSC%freq)==0) //now check if we can directly divide HSI
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{
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if(freq==INTOSC)
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{
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RCC->CFGR &= ~(0xF<<4);
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return freq;
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}
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for(i=1;i<8;i++)
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{
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if((freq<<i)==INTOSC)
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{
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RCC->CFGR &= ~(0xF<<4);
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RCC->CFGR |= ((0x8|i)<<4);
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return freq;
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}
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}
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}
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else
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return setPll(freq);
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}
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else //HSE used as sys clk
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{
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if((OSC0%freq)==0) //now check if we can directly divide HSI
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{
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if(freq==OSC0)
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{
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RCC->CFGR &= ~(0xF<<4);
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return freq;
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}
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for(i=1;i<8;i++)
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{
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if((freq<<i)==OSC0)
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{
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RCC->CFGR &= ~(0xF<<4);
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RCC->CFGR |= ((0x8|i)<<4);
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return freq;
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}
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}
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}
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else
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return setPll(freq);
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}
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}
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return 0;
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}
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void enable_FPU()
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{
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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__asm__("dsb");
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__asm__("isb");
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}
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