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/**
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* @file : lpc17xx_ssp.c
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* @brief : Contains all functions support for SSP firmware library on LPC17xx
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* @version : 1.0
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* @date : 9. April. 2009
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* @author : HieuNguyen
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**************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @addtogroup SSP
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* @{
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*/
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/* Includes ------------------------------------------------------------------- */
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#include "lpc17xx_ssp.h"
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#include "lpc17xx_clkpwr.h"
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/* If this source file built with example, the LPC17xx FW library configuration
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* file in each example directory ("lpc17xx_libcfg.h") must be included,
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* otherwise the default FW library configuration file must be included instead
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*/
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#ifdef __BUILD_WITH_EXAMPLE__
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#include "lpc17xx_libcfg.h"
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#else
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#include "lpc17xx_libcfg_default.h"
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#endif /* __BUILD_WITH_EXAMPLE__ */
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#ifdef _SSP
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/* Private Types -------------------------------------------------------------- */
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/** @defgroup SSP_Private_Types
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* @{
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*/
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/** @brief SSP device configuration structure type */
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typedef struct
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{
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int32_t dataword; /* Current data word: 0 - 8 bit; 1 - 16 bit */
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uint32_t txrx_setup; /* Transmission setup */
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void (*inthandler)(LPC_SSP_TypeDef *SSPx); /* Transmission interrupt handler */
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} SSP_CFG_T;
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/**
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* @}
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*/
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/* Private Variables ---------------------------------------------------------- */
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/* SSP configuration data */
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static SSP_CFG_T sspdat[2];
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/* Private Functions ---------------------------------------------------------- */
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/** @defgroup SSP_Private_Functions
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* @{
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*/
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/**
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* @brief Convert from SSP peripheral to number
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*/
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static int32_t SSP_getNum(LPC_SSP_TypeDef *SSPx){
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if (SSPx == LPC_SSP0) {
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return (0);
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} else if (SSPx == LPC_SSP1) {
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return (1);
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}
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return (-1);
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}
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/*********************************************************************//**
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* @brief Standard Private SSP Interrupt handler
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* @param SSPx: SSP peripheral definition, should be
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* SSP0 or SSP1.
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* @return None
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***********************************************************************/
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void SSP_IntHandler(LPC_SSP_TypeDef *SSPx)
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{
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SSP_DATA_SETUP_Type *xf_setup;
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uint16_t tmp;
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int32_t sspnum;
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// Disable interrupt
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SSPx->IMSC = 0;
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sspnum = SSP_getNum(SSPx);
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xf_setup = (SSP_DATA_SETUP_Type *)sspdat[sspnum].txrx_setup;
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// save status
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tmp = SSPx->RIS;
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xf_setup->status = tmp;
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// Check overrun error
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if (tmp & SSP_RIS_ROR){
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// Clear interrupt
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SSPx->ICR = SSP_RIS_ROR;
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// update status
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xf_setup->status |= SSP_STAT_ERROR;
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// Callback
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if (xf_setup->callback != NULL){
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xf_setup->callback();
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}
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return;
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}
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if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)){
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/* check if RX FIFO contains data */
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while ((SSPx->SR & SSP_SR_RNE) && (xf_setup->rx_cnt != xf_setup->length)){
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// Read data from SSP data
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tmp = SSP_ReceiveData(SSPx);
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// Store data to destination
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if (xf_setup->rx_data != NULL)
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{
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if (sspdat[sspnum].dataword == 0){
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*(uint8_t *)((uint32_t)xf_setup->rx_data + xf_setup->rx_cnt) = (uint8_t) tmp;
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} else {
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*(uint16_t *)((uint32_t)xf_setup->rx_data + xf_setup->rx_cnt) = (uint16_t) tmp;
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}
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}
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// Increase counter
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if (sspdat[sspnum].dataword == 0){
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xf_setup->rx_cnt++;
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} else {
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xf_setup->rx_cnt += 2;
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}
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}
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while ((SSPx->SR & SSP_SR_TNF) && (xf_setup->tx_cnt != xf_setup->length)){
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// Write data to buffer
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if(xf_setup->tx_data == NULL){
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if (sspdat[sspnum].dataword == 0){
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SSP_SendData(SSPx, 0xFF);
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xf_setup->tx_cnt++;
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} else {
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SSP_SendData(SSPx, 0xFFFF);
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xf_setup->tx_cnt += 2;
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}
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} else {
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if (sspdat[sspnum].dataword == 0){
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SSP_SendData(SSPx, (*(uint8_t *)((uint32_t)xf_setup->tx_data + xf_setup->tx_cnt)));
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xf_setup->tx_cnt++;
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} else {
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SSP_SendData(SSPx, (*(uint16_t *)((uint32_t)xf_setup->tx_data + xf_setup->tx_cnt)));
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xf_setup->tx_cnt += 2;
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}
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}
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// Check overrun error
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if ((tmp = SSPx->RIS) & SSP_RIS_ROR){
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// update status
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xf_setup->status |= SSP_STAT_ERROR;
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// Callback
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if (xf_setup->callback != NULL){
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xf_setup->callback();
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}
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return;
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}
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// Check for any data available in RX FIFO
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while ((SSPx->SR & SSP_SR_RNE) && (xf_setup->rx_cnt != xf_setup->length)){
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// Read data from SSP data
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tmp = SSP_ReceiveData(SSPx);
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// Store data to destination
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if (xf_setup->rx_data != NULL)
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{
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if (sspdat[sspnum].dataword == 0){
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*(uint8_t *)((uint32_t)xf_setup->rx_data + xf_setup->rx_cnt) = (uint8_t) tmp;
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} else {
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*(uint16_t *)((uint32_t)xf_setup->rx_data + xf_setup->rx_cnt) = (uint16_t) tmp;
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}
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}
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// Increase counter
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if (sspdat[sspnum].dataword == 0){
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xf_setup->rx_cnt++;
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} else {
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xf_setup->rx_cnt += 2;
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}
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}
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}
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}
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// If there more data to sent or receive
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if ((xf_setup->rx_cnt != xf_setup->length) || (xf_setup->tx_cnt != xf_setup->length)){
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// Enable all interrupt
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SSPx->IMSC = SSP_IMSC_BITMASK;
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} else {
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// Save status
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xf_setup->status = SSP_STAT_DONE;
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// Callback
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if (xf_setup->callback != NULL){
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xf_setup->callback();
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}
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}
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}
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @addtogroup SSP_Public_Functions
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* @{
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*/
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/*********************************************************************//**
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* @brief Setup clock rate for SSP device
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* @param[in] SSPx SSP peripheral definition, should be
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* SSP0 or SSP1.
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* @param[in] target_clock : clock of SSP (Hz)
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* @return None
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***********************************************************************/
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void SSP_SetClock (LPC_SSP_TypeDef *SSPx, uint32_t target_clock)
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{
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uint32_t prescale, cr0_div, cmp_clk, ssp_clk;
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CHECK_PARAM(PARAM_SSPx(SSPx));
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/* The SSP clock is derived from the (main system oscillator / 2),
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so compute the best divider from that clock */
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if (SSPx == LPC_SSP0){
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ssp_clk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_SSP0);
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} else if (SSPx == LPC_SSP1) {
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ssp_clk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_SSP1);
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} else {
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return;
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}
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/* Find closest divider to get at or under the target frequency.
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Use smallest prescale possible and rely on the divider to get
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the closest target frequency */
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cr0_div = 0;
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cmp_clk = 0xFFFFFFFF;
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prescale = 2;
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while (cmp_clk > target_clock)
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{
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cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
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if (cmp_clk > target_clock)
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{
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cr0_div++;
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if (cr0_div > 0xFF)
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{
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cr0_div = 0;
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prescale += 2;
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}
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}
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}
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/* Write computed prescaler and divider back to register */
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SSPx->CR0 &= (~SSP_CR0_SCR(0xFF)) & SSP_CR0_BITMASK;
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SSPx->CR0 |= (SSP_CR0_SCR(cr0_div)) & SSP_CR0_BITMASK;
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SSPx->CPSR = prescale & SSP_CPSR_BITMASK;
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}
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/*********************************************************************//**
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* @brief De-initializes the SSPx peripheral registers to their
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* default reset values.
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* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
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* @return None
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**********************************************************************/
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void SSP_DeInit(LPC_SSP_TypeDef* SSPx)
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{
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CHECK_PARAM(PARAM_SSPx(SSPx));
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if (SSPx == LPC_SSP0){
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/* Set up clock and power for SSP0 module */
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CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP0, DISABLE);
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} else if (SSPx == LPC_SSP1) {
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/* Set up clock and power for SSP1 module */
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CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP1, DISABLE);
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}
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}
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/********************************************************************//**
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* @brief Initializes the SSPx peripheral according to the specified
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* parameters in the SSP_ConfigStruct.
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* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
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* @param[in] SSP_ConfigStruct Pointer to a SSP_CFG_Type structure
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* that contains the configuration information for the
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* specified SSP peripheral.
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* @return None
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*********************************************************************/
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void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct)
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{
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uint32_t tmp;
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CHECK_PARAM(PARAM_SSPx(SSPx));
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if(SSPx == LPC_SSP0) {
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/* Set up clock and power for SSP0 module */
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CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP0, ENABLE);
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} else if(SSPx == LPC_SSP1) {
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/* Set up clock and power for SSP1 module */
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CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP1, ENABLE);
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} else {
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return;
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}
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/* Configure SSP, interrupt is disable, LoopBack mode is disable,
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* SSP is disable, Slave output is disable as default
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*/
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tmp = ((SSP_ConfigStruct->CPHA) | (SSP_ConfigStruct->CPOL) \
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| (SSP_ConfigStruct->FrameFormat) | (SSP_ConfigStruct->Databit))
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& SSP_CR0_BITMASK;
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// write back to SSP control register
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SSPx->CR0 = tmp;
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tmp = SSP_getNum(SSPx);
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if (SSP_ConfigStruct->Databit > SSP_DATABIT_8){
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sspdat[tmp].dataword = 1;
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} else {
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sspdat[tmp].dataword = 0;
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}
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tmp = SSP_ConfigStruct->Mode & SSP_CR1_BITMASK;
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// Write back to CR1
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SSPx->CR1 = tmp;
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// Set clock rate for SSP peripheral
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SSP_SetClock(SSPx, SSP_ConfigStruct->ClockRate);
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}
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/*****************************************************************************//**
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* @brief Fills each SSP_InitStruct member with its default value:
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* - CPHA = SSP_CPHA_FIRST
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* - CPOL = SSP_CPOL_HI
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* - ClockRate = 1000000
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* - Databit = SSP_DATABIT_8
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* - Mode = SSP_MASTER_MODE
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* - FrameFormat = SSP_FRAME_SSP
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* @param[in] SSP_InitStruct Pointer to a SSP_CFG_Type structure
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* which will be initialized.
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* @return None
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*******************************************************************************/
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void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct)
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{
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SSP_InitStruct->CPHA = SSP_CPHA_FIRST;
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SSP_InitStruct->CPOL = SSP_CPOL_HI;
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SSP_InitStruct->ClockRate = 1000000;
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SSP_InitStruct->Databit = SSP_DATABIT_8;
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SSP_InitStruct->Mode = SSP_MASTER_MODE;
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SSP_InitStruct->FrameFormat = SSP_FRAME_SPI;
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}
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/*********************************************************************//**
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* @brief Enable or disable SSP peripheral's operation
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* @param[in] SSPx SSP peripheral, should be SSP0 or SSP1
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* @param[in] NewState New State of SSPx peripheral's operation
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* @return none
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**********************************************************************/
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void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState)
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{
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CHECK_PARAM(PARAM_SSPx(SSPx));
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CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
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if (NewState == ENABLE)
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{
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SSPx->CR1 |= SSP_CR1_SSP_EN;
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}
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else
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{
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SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
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}
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}
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/*********************************************************************//**
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* @brief Enable or disable Loop Back mode function in SSP peripheral
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* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
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* @param[in] NewState New State of Loop Back mode, should be:
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* - ENABLE: Enable this function
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* - DISABLE: Disable this function
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* @return None
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**********************************************************************/
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void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState)
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{
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CHECK_PARAM(PARAM_SSPx(SSPx));
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CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
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if (NewState == ENABLE)
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{
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SSPx->CR1 |= SSP_CR1_LBM_EN;
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}
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else
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{
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SSPx->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
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}
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}
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/*********************************************************************//**
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* @brief Enable or disable Slave Output function in SSP peripheral
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* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
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* @param[in] NewState New State of Slave Output function, should be:
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* - ENABLE: Slave Output in normal operation
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* - DISABLE: Slave Output is disabled. This blocks
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* SSP controller from driving the transmit data
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* line (MISO)
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* Note: This function is available when SSP peripheral in Slave mode
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* @return None
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**********************************************************************/
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void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState)
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{
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|
|
CHECK_PARAM(PARAM_SSPx(SSPx));
|
|
|
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
|
|
|
|
|
|
if (NewState == ENABLE)
|
|
|
{
|
|
|
SSPx->CR1 &= (~SSP_CR1_SO_DISABLE) & SSP_CR1_BITMASK;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
SSPx->CR1 |= SSP_CR1_SO_DISABLE;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************//**
|
|
|
* @brief Transmit a single data through SSPx peripheral
|
|
|
* @param[in] SSPx SSP peripheral selected, should be SSP
|
|
|
* @param[in] Data Data to transmit (must be 16 or 8-bit long,
|
|
|
* this depend on SSP data bit number configured)
|
|
|
* @return none
|
|
|
**********************************************************************/
|
|
|
void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data)
|
|
|
{
|
|
|
CHECK_PARAM(PARAM_SSPx(SSPx));
|
|
|
|
|
|
SSPx->DR = SSP_DR_BITMASK(Data);
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************//**
|
|
|
* @brief Receive a single data from SSPx peripheral
|
|
|
* @param[in] SSPx SSP peripheral selected, should be SSP
|
|
|
* @return Data received (16-bit long)
|
|
|
**********************************************************************/
|
|
|
uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx)
|
|
|
{
|
|
|
CHECK_PARAM(PARAM_SSPx(SSPx));
|
|
|
|
|
|
return ((uint16_t) (SSP_DR_BITMASK(SSPx->DR)));
|
|
|
}
|
|
|
|
|
|
/*********************************************************************//**
|
|
|
* @brief SSP Read write data function
|
|
|
* @param[in] SSPx Pointer to SSP peripheral, should be SSP0 or SSP1
|
|
|
* @param[in] dataCfg Pointer to a SSP_DATA_SETUP_Type structure that
|
|
|
* contains specified information about transmit
|
|
|
* data configuration.
|
|
|
* @param[in] xfType Transfer type, should be:
|
|
|
* - SSP_TRANSFER_POLLING: Polling mode
|
|
|
* - SSP_TRANSFER_INTERRUPT: Interrupt mode
|
|
|
* @return Actual Data length has been transferred in polling mode.
|
|
|
* In interrupt mode, always return (0)
|
|
|
* Return (-1) if error.
|
|
|
* Note: This function can be used in both master and slave mode.
|
|
|
***********************************************************************/
|
|
|
int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
|
|
|
SSP_TRANSFER_Type xfType)
|
|
|
{
|
|
|
uint8_t *rdata8;
|
|
|
uint8_t *wdata8;
|
|
|
uint16_t *rdata16;
|
|
|
uint16_t *wdata16;
|
|
|
uint32_t stat;
|
|
|
uint32_t tmp;
|
|
|
int32_t sspnum;
|
|
|
int32_t dataword;
|
|
|
|
|
|
dataCfg->rx_cnt = 0;
|
|
|
dataCfg->tx_cnt = 0;
|
|
|
dataCfg->status = 0;
|
|
|
|
|
|
|
|
|
/* Clear all remaining data in RX FIFO */
|
|
|
while (SSPx->SR & SSP_SR_RNE){
|
|
|
tmp = (uint32_t) SSP_ReceiveData(SSPx);
|
|
|
}
|
|
|
|
|
|
// Clear status
|
|
|
SSPx->ICR = SSP_ICR_BITMASK;
|
|
|
|
|
|
sspnum = SSP_getNum(SSPx);
|
|
|
dataword = sspdat[sspnum].dataword;
|
|
|
|
|
|
// Polling mode ----------------------------------------------------------------------
|
|
|
if (xfType == SSP_TRANSFER_POLLING){
|
|
|
if (dataword == 0){
|
|
|
rdata8 = (uint8_t *)dataCfg->rx_data;
|
|
|
wdata8 = (uint8_t *)dataCfg->tx_data;
|
|
|
} else {
|
|
|
rdata16 = (uint16_t *)dataCfg->rx_data;
|
|
|
wdata16 = (uint16_t *)dataCfg->tx_data;
|
|
|
}
|
|
|
while ((dataCfg->tx_cnt != dataCfg->length) || (dataCfg->rx_cnt != dataCfg->length)){
|
|
|
if ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt != dataCfg->length)){
|
|
|
// Write data to buffer
|
|
|
if(dataCfg->tx_data == NULL){
|
|
|
if (dataword == 0){
|
|
|
SSP_SendData(SSPx, 0xFF);
|
|
|
dataCfg->tx_cnt++;
|
|
|
} else {
|
|
|
SSP_SendData(SSPx, 0xFFFF);
|
|
|
dataCfg->tx_cnt += 2;
|
|
|
}
|
|
|
} else {
|
|
|
if (dataword == 0){
|
|
|
SSP_SendData(SSPx, *wdata8);
|
|
|
wdata8++;
|
|
|
dataCfg->tx_cnt++;
|
|
|
} else {
|
|
|
SSP_SendData(SSPx, *wdata16);
|
|
|
wdata16++;
|
|
|
dataCfg->tx_cnt += 2;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
// Check overrun error
|
|
|
if ((stat = SSPx->RIS) & SSP_RIS_ROR){
|
|
|
// save status and return
|
|
|
dataCfg->status = stat | SSP_STAT_ERROR;
|
|
|
return (-1);
|
|
|
}
|
|
|
|
|
|
// Check for any data available in RX FIFO
|
|
|
while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt != dataCfg->length)){
|
|
|
// Read data from SSP data
|
|
|
tmp = SSP_ReceiveData(SSPx);
|
|
|
|
|
|
// Store data to destination
|
|
|
if (dataCfg->rx_data != NULL)
|
|
|
{
|
|
|
if (dataword == 0){
|
|
|
*(rdata8) = (uint8_t) tmp;
|
|
|
rdata8++;
|
|
|
} else {
|
|
|
*(rdata16) = (uint16_t) tmp;
|
|
|
rdata16++;
|
|
|
}
|
|
|
}
|
|
|
// Increase counter
|
|
|
if (dataword == 0){
|
|
|
dataCfg->rx_cnt++;
|
|
|
} else {
|
|
|
dataCfg->rx_cnt += 2;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
// save status
|
|
|
dataCfg->status = SSP_STAT_DONE;
|
|
|
|
|
|
if (dataCfg->tx_data != NULL){
|
|
|
return dataCfg->tx_cnt;
|
|
|
} else if (dataCfg->rx_data != NULL){
|
|
|
return dataCfg->rx_cnt;
|
|
|
} else {
|
|
|
return (0);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
// Interrupt mode ----------------------------------------------------------------------
|
|
|
else if (xfType == SSP_TRANSFER_INTERRUPT){
|
|
|
sspdat[sspnum].inthandler = SSP_IntHandler;
|
|
|
sspdat[sspnum].txrx_setup = (uint32_t)dataCfg;
|
|
|
|
|
|
while ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt != dataCfg->length)){
|
|
|
// Write data to buffer
|
|
|
if(dataCfg->tx_data == NULL){
|
|
|
if (sspdat[sspnum].dataword == 0){
|
|
|
SSP_SendData(SSPx, 0xFF);
|
|
|
dataCfg->tx_cnt++;
|
|
|
} else {
|
|
|
SSP_SendData(SSPx, 0xFFFF);
|
|
|
dataCfg->tx_cnt += 2;
|
|
|
}
|
|
|
} else {
|
|
|
if (sspdat[sspnum].dataword == 0){
|
|
|
SSP_SendData(SSPx, (*(uint8_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));
|
|
|
dataCfg->tx_cnt++;
|
|
|
} else {
|
|
|
SSP_SendData(SSPx, (*(uint16_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));
|
|
|
dataCfg->tx_cnt += 2;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
// Check error
|
|
|
if ((stat = SSPx->RIS) & SSP_RIS_ROR){
|
|
|
// save status and return
|
|
|
dataCfg->status = stat | SSP_STAT_ERROR;
|
|
|
return (-1);
|
|
|
}
|
|
|
|
|
|
// Check for any data available in RX FIFO
|
|
|
while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt != dataCfg->length)){
|
|
|
// Read data from SSP data
|
|
|
tmp = SSP_ReceiveData(SSPx);
|
|
|
|
|
|
// Store data to destination
|
|
|
if (dataCfg->rx_data != NULL)
|
|
|
{
|
|
|
if (sspdat[sspnum].dataword == 0){
|
|
|
*(uint8_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint8_t) tmp;
|
|
|
} else {
|
|
|
*(uint16_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint16_t) tmp;
|
|
|
}
|
|
|
}
|
|
|
// Increase counter
|
|
|
if (sspdat[sspnum].dataword == 0){
|
|
|
dataCfg->rx_cnt++;
|
|
|
} else {
|
|
|
dataCfg->rx_cnt += 2;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
// If there more data to sent or receive
|
|
|
if ((dataCfg->rx_cnt != dataCfg->length) || (dataCfg->tx_cnt != dataCfg->length)){
|
|
|
// Enable all interrupt
|
|
|
SSPx->IMSC = SSP_IMSC_BITMASK;
|
|
|
} else {
|
|
|
// Save status
|
|
|
dataCfg->status = SSP_STAT_DONE;
|
|
|
}
|
|
|
return (0);
|
|
|
}
|
|
|
|
|
|
return (-1);
|
|
|
}
|
|
|
|
|
|
/*********************************************************************//**
|
|
|
* @brief Checks whether the specified SSP status flag is set or not
|
|
|
* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
|
|
|
* @param[in] FlagType Type of flag to check status, should be one
|
|
|
* of following:
|
|
|
* - SSP_STAT_TXFIFO_EMPTY: TX FIFO is empty
|
|
|
* - SSP_STAT_TXFIFO_NOTFULL: TX FIFO is not full
|
|
|
* - SSP_STAT_RXFIFO_NOTEMPTY: RX FIFO is not empty
|
|
|
* - SSP_STAT_RXFIFO_FULL: RX FIFO is full
|
|
|
* - SSP_STAT_BUSY: SSP peripheral is busy
|
|
|
* @return New State of specified SSP status flag
|
|
|
**********************************************************************/
|
|
|
FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType)
|
|
|
{
|
|
|
CHECK_PARAM(PARAM_SSPx(SSPx));
|
|
|
CHECK_PARAM(PARAM_SSP_STAT(FlagType));
|
|
|
|
|
|
return ((SSPx->SR & FlagType) ? SET : RESET);
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************//**
|
|
|
* @brief Enable or disable specified interrupt type in SSP peripheral
|
|
|
* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
|
|
|
* @param[in] IntType Interrupt type in SSP peripheral, should be:
|
|
|
* - SSP_INTCFG_ROR: Receive Overrun interrupt
|
|
|
* - SSP_INTCFG_RT: Receive Time out interrupt
|
|
|
* - SSP_INTCFG_RX: RX FIFO is at least half full interrupt
|
|
|
* - SSP_INTCFG_TX: TX FIFO is at least half empty interrupt
|
|
|
* @param[in] NewState New State of specified interrupt type, should be:
|
|
|
* - ENABLE: Enable this interrupt type
|
|
|
* - DISABLE: Disable this interrupt type
|
|
|
* @return None
|
|
|
**********************************************************************/
|
|
|
void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState)
|
|
|
{
|
|
|
CHECK_PARAM(PARAM_SSPx(SSPx));
|
|
|
CHECK_PARAM(PARAM_SSP_INTCFG(IntType));
|
|
|
|
|
|
if (NewState == ENABLE)
|
|
|
{
|
|
|
SSPx->IMSC |= IntType;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
SSPx->IMSC &= (~IntType) & SSP_IMSC_BITMASK;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
|
|
|
/*********************************************************************//**
|
|
|
* @brief Check whether the specified Raw interrupt status flag is
|
|
|
* set or not
|
|
|
* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
|
|
|
* @param[in] RawIntType Raw Interrupt Type, should be:
|
|
|
* - SSP_INTSTAT_RAW_ROR: Receive Overrun interrupt
|
|
|
* - SSP_INTSTAT_RAW_RT: Receive Time out interrupt
|
|
|
* - SSP_INTSTAT_RAW_RX: RX FIFO is at least half full interrupt
|
|
|
* - SSP_INTSTAT_RAW_TX: TX FIFO is at least half empty interrupt
|
|
|
* @return New State of specified Raw interrupt status flag in SSP peripheral
|
|
|
* Note: Enabling/Disabling specified interrupt in SSP peripheral does not
|
|
|
* effect to Raw Interrupt Status flag.
|
|
|
**********************************************************************/
|
|
|
IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType)
|
|
|
{
|
|
|
CHECK_PARAM(PARAM_SSPx(SSPx));
|
|
|
CHECK_PARAM(PARAM_SSP_INTSTAT_RAW(RawIntType));
|
|
|
|
|
|
return ((SSPx->RIS & RawIntType) ? SET : RESET);
|
|
|
}
|
|
|
|
|
|
|
|
|
/*********************************************************************//**
|
|
|
* @brief Check whether the specified interrupt status flag is
|
|
|
* set or not
|
|
|
* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
|
|
|
* @param[in] IntType Raw Interrupt Type, should be:
|
|
|
* - SSP_INTSTAT_ROR: Receive Overrun interrupt
|
|
|
* - SSP_INTSTAT_RT: Receive Time out interrupt
|
|
|
* - SSP_INTSTAT_RX: RX FIFO is at least half full interrupt
|
|
|
* - SSP_INTSTAT_TX: TX FIFO is at least half empty interrupt
|
|
|
* @return New State of specified interrupt status flag in SSP peripheral
|
|
|
* Note: Enabling/Disabling specified interrupt in SSP peripheral effects
|
|
|
* to Interrupt Status flag.
|
|
|
**********************************************************************/
|
|
|
IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType)
|
|
|
{
|
|
|
CHECK_PARAM(PARAM_SSPx(SSPx));
|
|
|
CHECK_PARAM(PARAM_SSP_INTSTAT(IntType));
|
|
|
|
|
|
return ((SSPx->MIS & IntType) ? SET :RESET);
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************//**
|
|
|
* @brief Clear specified interrupt pending in SSP peripheral
|
|
|
* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
|
|
|
* @param[in] IntType Interrupt pending to clear, should be:
|
|
|
* - SSP_INTCLR_ROR: clears the "frame was received when
|
|
|
* RxFIFO was full" interrupt.
|
|
|
* - SSP_INTCLR_RT: clears the "Rx FIFO was not empty and
|
|
|
* has not been read for a timeout period" interrupt.
|
|
|
* @return None
|
|
|
**********************************************************************/
|
|
|
void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType)
|
|
|
{
|
|
|
CHECK_PARAM(PARAM_SSPx(SSPx));
|
|
|
CHECK_PARAM(PARAM_SSP_INTCLR(IntType));
|
|
|
|
|
|
SSPx->ICR = IntType;
|
|
|
}
|
|
|
|
|
|
/*********************************************************************//**
|
|
|
* @brief Enable/Disable DMA function for SSP peripheral
|
|
|
* @param[in] SSPx SSP peripheral selected, should be SSP0 or SSP1
|
|
|
* @param[in] DMAMode Type of DMA, should be:
|
|
|
* - SSP_DMA_TX: DMA for the transmit FIFO
|
|
|
* - SSP_DMA_RX: DMA for the Receive FIFO
|
|
|
* @param[in] NewState New State of DMA function on SSP peripheral,
|
|
|
* should be:
|
|
|
* - ENALBE: Enable this function
|
|
|
* - DISABLE: Disable this function
|
|
|
* @return None
|
|
|
**********************************************************************/
|
|
|
void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState)
|
|
|
{
|
|
|
CHECK_PARAM(PARAM_SSPx(SSPx));
|
|
|
CHECK_PARAM(PARAM_SSP_DMA(DMAMode));
|
|
|
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
|
|
|
|
|
|
if (NewState == ENABLE)
|
|
|
{
|
|
|
SSPx->DMACR |= DMAMode;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
SSPx->DMACR &= (~DMAMode) & SSP_DMA_BITMASK;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Standard SSP0 Interrupt handler
|
|
|
* @param[in] None
|
|
|
* @return None
|
|
|
*/
|
|
|
void SSP0_StdIntHandler(void)
|
|
|
{
|
|
|
// Call relevant handler
|
|
|
sspdat[0].inthandler(LPC_SSP0);
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Standard SSP1 Interrupt handler
|
|
|
* @param[in] None
|
|
|
* @return None
|
|
|
*/
|
|
|
void SSP1_StdIntHandler(void)
|
|
|
{
|
|
|
// Call relevant handler
|
|
|
sspdat[1].inthandler(LPC_SSP1);
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
#endif /* _SSP */
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/* --------------------------------- End Of File ------------------------------ */
|
|
|
|
|
|
|
