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/***********************************************************************//**
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* @file : lpc17xx_qei.h
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* @brief : Contains all macro definitions and function prototypes
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* support for QEI firmware library on LPC17xx
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* @version : 1.0
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* @date : 26. May. 2009
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* @author : HieuNguyen
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**************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**************************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup QEI
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* @ingroup LPC1700CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef LPC17XX_QEI_H_
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#define LPC17XX_QEI_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC17xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup QEI_Private_Macros
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* @{
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*/
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/** @defgroup QEI_REGISTER_BIT_DEFINITIONS
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* @{
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*/
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/* Quadrature Encoder Interface Control Register Definition --------------------- */
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/* QEI Control register */
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#define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
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#define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
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#define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
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#define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
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#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
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/* QEI Configuration register */
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#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
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#define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
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#define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
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#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
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#define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
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/* QEI Status register */
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#define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
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#define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
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/* Quadrature Encoder Interface Position, index and timer Register Definitions --- */
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/* QEI Position register */
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/* QEI Maximum Position register */
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/* QEI Position Compare register 0 */
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/* QEI Position Compare register 1 */
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/* QEI Position Compare register 2 */
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/* QEI Index Count register */
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/* QEI Index Compare register */
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/* QEI Timer Reload register */
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/* QEI Timer register */
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/* QEI Velocity register */
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/* QEI Velocity Capture register */
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/* QEI Velocity Compare register */
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/* QEI Digital Filter register */
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/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
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/* QEI Interrupt Status register */
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#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
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#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
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#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
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#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
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#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
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#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
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#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
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current position */
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#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
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current position */
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#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
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current position */
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#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
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index count */
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#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
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both the POS0_Int bit is set and the REV_Int is set */
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#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
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both the POS1_Int bit is set and the REV_Int is set */
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#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
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both the POS2_Int bit is set and the REV_Int is set */
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#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
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/* QEI Interrupt Set register */
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#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
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#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
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#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
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#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
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#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
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#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
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#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
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current position */
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#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
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current position */
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#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
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current position */
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#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
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index count */
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#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
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#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
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#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
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#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
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/* QEI Interrupt Clear register */
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#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
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#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
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#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
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#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
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#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
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#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
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#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
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current position */
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#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
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current position */
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#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
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current position */
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#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
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index count */
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#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
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#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
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#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
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#define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */
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/* QEI Interrupt Enable register */
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#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
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#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
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#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
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#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
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#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
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#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
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#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
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current position */
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#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
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current position */
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#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
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current position */
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#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
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index count */
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#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
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#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
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#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
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#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
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/* QEI Interrupt Enable Set register */
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#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
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#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
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#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
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#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
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#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
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#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
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#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
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current position */
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#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
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current position */
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#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
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current position */
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#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
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index count */
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#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
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#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
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#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
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#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
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/* QEI Interrupt Enable Clear register */
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#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
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#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
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#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
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#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
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#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
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#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
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#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
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current position */
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#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
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current position */
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#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
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current position */
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#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
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index count */
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#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
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#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
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#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
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#define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Public Types --------------------------------------------------------------- */
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/** @defgroup QEI_Public_Types
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* @{
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*/
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/**
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* @brief QEI Configuration structure type definition
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*/
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typedef struct {
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uint32_t DirectionInvert :1; /**< Direction invert option:
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- QEI_DIRINV_NONE: QEI Direction is normal
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- QEI_DIRINV_CMPL: QEI Direction is complemented
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*/
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uint32_t SignalMode :1; /**< Signal mode Option:
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- QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
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- QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
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*/
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uint32_t CaptureMode :1; /**< Capture Mode Option:
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- QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
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- QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
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*/
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uint32_t InvertIndex :1; /**< Invert Index Option:
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- QEI_INVINX_NONE: the sense of the index input is normal
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- QEI_INVINX_EN: inverts the sense of the index input
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*/
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} QEI_CFG_Type;
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/**
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* @brief Timer Reload Configuration structure type definition
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*/
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typedef struct {
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uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be:
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- QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
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- QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
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*/
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uint8_t Reserved[3];
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uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched
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with Velocity Timer Reload Option
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*/
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} QEI_RELOADCFG_Type;
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/**
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* @}
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*/
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup QEI_Public_Macros
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* @{
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*/
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#define PARAM_QEIx(n) ((n==LPC_QEI))
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/* QEI Reset types */
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#define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
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#define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
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#define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
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#define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
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#define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \
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|| (n==QEI_RESET_POSOnIDX) \
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|| (n==QEI_RESET_VEL) \
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|| (n==QEI_RESET_IDX))
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/* QEI Direction Invert Type Option */
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#define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
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#define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
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#define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))
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/* QEI Signal Mode Option */
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#define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
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#define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
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#define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))
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/* QEI Capture Mode Option */
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#define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
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#define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
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#define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))
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/* QEI Invert Index Signal Option */
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#define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
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#define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
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#define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))
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/* QEI timer reload option */
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#define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
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#define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
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#define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))
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/* QEI Flag Status type */
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#define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
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#define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR))
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/* QEI Compare Position channel option */
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#define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
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#define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
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#define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
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#define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))
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/* QEI interrupt flag type */
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#define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
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#define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
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#define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
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#define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
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#define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
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#define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
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#define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
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current position interrupt */
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#define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
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current position interrupt */
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#define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
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current position interrupt */
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#define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
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index count interrupt */
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#define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
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#define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
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#define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
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#define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \
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|| (n==QEI_INTFLAG_TIM_Int) \
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|| (n==QEI_INTFLAG_VELC_Int) \
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|| (n==QEI_INTFLAG_DIR_Int) \
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|| (n==QEI_INTFLAG_ERR_Int) \
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|| (n==QEI_INTFLAG_ENCLK_Int) \
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|| (n==QEI_INTFLAG_POS0_Int) \
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|| (n==QEI_INTFLAG_POS1_Int) \
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|| (n==QEI_INTFLAG_POS2_Int) \
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|| (n==QEI_INTFLAG_REV_Int) \
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|| (n==QEI_INTFLAG_POS0REV_Int) \
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|| (n==QEI_INTFLAG_POS1REV_Int) \
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|| (n==QEI_INTFLAG_POS2REV_Int))
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @defgroup QEI_Public_Functions
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* @{
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*/
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void QEI_Reset(LPC_QEI_TypeDef *QEIx, uint32_t ulResetType);
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void QEI_Init(LPC_QEI_TypeDef *QEIx, QEI_CFG_Type *QEI_ConfigStruct);
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void QEI_ConfigStructInit(QEI_CFG_Type *QIE_InitStruct);
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void QEI_DeInit(LPC_QEI_TypeDef *QEIx);
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FlagStatus QEI_GetStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulFlagType);
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uint32_t QEI_GetPosition(LPC_QEI_TypeDef *QEIx);
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void QEI_SetMaxPosition(LPC_QEI_TypeDef *QEIx, uint32_t ulMaxPos);
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void QEI_SetPositionComp(LPC_QEI_TypeDef *QEIx, uint8_t bPosCompCh, uint32_t ulPosComp);
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uint32_t QEI_GetIndex(LPC_QEI_TypeDef *QEIx);
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void QEI_SetIndexComp(LPC_QEI_TypeDef *QEIx, uint32_t ulIndexComp);
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void QEI_SetTimerReload(LPC_QEI_TypeDef *QEIx, QEI_RELOADCFG_Type *QEIReloadStruct);
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uint32_t QEI_GetTimer(LPC_QEI_TypeDef *QEIx);
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uint32_t QEI_GetVelocity(LPC_QEI_TypeDef *QEIx);
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uint32_t QEI_GetVelocityCap(LPC_QEI_TypeDef *QEIx);
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void QEI_SetVelocityComp(LPC_QEI_TypeDef *QEIx, uint32_t ulVelComp);
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void QEI_SetDigiFilter(LPC_QEI_TypeDef *QEIx, uint32_t ulSamplingPulse);
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FlagStatus QEI_GetIntStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
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void QEI_IntCmd(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType, FunctionalState NewState);
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void QEI_IntSet(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
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void QEI_IntClear(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
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uint32_t QEI_CalculateRPM(LPC_QEI_TypeDef *QEIx, uint32_t ulVelCapValue, uint32_t ulPPR);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* LPC17XX_QEI_H_ */
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/**
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* @}
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*/
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/* --------------------------------- End Of File ------------------------------ */
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