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/***********************************************************************//**
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* @file : lpc17xx_i2c.h
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* @brief : Contains all macro definitions and function prototypes
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* support for I2C firmware library on LPC17xx
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* @version : 1.0
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* @date : 13. Apr. 2009
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* @author : HieuNguyen
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**************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**************************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup I2C
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* @ingroup LPC1700CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef LPC17XX_I2C_H_
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#define LPC17XX_I2C_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC17xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup I2C_Private_Macros
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* @{
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*/
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/** @defgroup I2C_REGISTER_BIT_DEFINITIONS
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* @{
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*/
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/*******************************************************************//**
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* I2C Control Set register description
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*********************************************************************/
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#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
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#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
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#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
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#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
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#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
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/*******************************************************************//**
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* I2C Control Clear register description
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*********************************************************************/
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/** Assert acknowledge Clear bit */
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#define I2C_I2CONCLR_AAC ((1<<2))
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/** I2C interrupt Clear bit */
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#define I2C_I2CONCLR_SIC ((1<<3))
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/** START flag Clear bit */
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#define I2C_I2CONCLR_STAC ((1<<5))
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/** I2C interface Disable bit */
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#define I2C_I2CONCLR_I2ENC ((1<<6))
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/********************************************************************//**
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* I2C Status Code definition (I2C Status register)
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*********************************************************************/
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/* Return Code in I2C status register */
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#define I2C_STAT_CODE_BITMASK ((0xF8))
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/* I2C return status code definitions ----------------------------- */
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/** No relevant information */
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#define I2C_I2STAT_NO_INF ((0xF8))
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/* Master transmit mode -------------------------------------------- */
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/** A start condition has been transmitted */
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#define I2C_I2STAT_M_TX_START ((0x08))
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/** A repeat start condition has been transmitted */
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#define I2C_I2STAT_M_TX_RESTART ((0x10))
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/** SLA+W has been transmitted, ACK has been received */
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#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
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/** SLA+W has been transmitted, NACK has been received */
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#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
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/** Data has been transmitted, ACK has been received */
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#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
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/** Data has been transmitted, NACK has been received */
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#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
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/** Arbitration lost in SLA+R/W or Data bytes */
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#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
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/* Master receive mode -------------------------------------------- */
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/** A start condition has been transmitted */
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#define I2C_I2STAT_M_RX_START ((0x08))
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/** A repeat start condition has been transmitted */
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#define I2C_I2STAT_M_RX_RESTART ((0x10))
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/** Arbitration lost */
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#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
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/** SLA+R has been transmitted, ACK has been received */
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#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
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/** SLA+R has been transmitted, NACK has been received */
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#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
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/** Data has been received, ACK has been returned */
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#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
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/** Data has been received, NACK has been return */
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#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
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/* Slave receive mode -------------------------------------------- */
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/** Own slave address has been received, ACK has been returned */
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#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
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/** Arbitration lost in SLA+R/W as master */
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#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
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/** Own SLA+W has been received, ACK returned */
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//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
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/** General call address has been received, ACK has been returned */
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#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
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/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
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#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
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/** General call address has been received, ACK has been returned */
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//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
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/** Previously addressed with own SLV address;
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* Data has been received, ACK has been return */
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#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
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/** Previously addressed with own SLA;
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* Data has been received and NOT ACK has been return */
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#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
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/** Previously addressed with General Call;
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* Data has been received and ACK has been return */
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#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
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/** Previously addressed with General Call;
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* Data has been received and NOT ACK has been return */
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#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
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/** A STOP condition or repeated START condition has
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* been received while still addressed as SLV/REC
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* (Slave Receive) or SLV/TRX (Slave Transmit) */
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#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
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/** Slave transmit mode */
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/** Own SLA+R has been received, ACK has been returned */
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#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
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/** Arbitration lost in SLA+R/W as master */
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#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
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/** Own SLA+R has been received, ACK has been returned */
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//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
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/** Data has been transmitted, ACK has been received */
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#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
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/** Data has been transmitted, NACK has been received */
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#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
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/** Last data byte in I2DAT has been transmitted (AA = 0);
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ACK has been received */
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#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
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/** Time out in case of using I2C slave mode */
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#define I2C_SLAVE_TIME_OUT 0x10000UL
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/********************************************************************//**
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* I2C Data register definition
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*********************************************************************/
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/** Mask for I2DAT register*/
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#define I2C_I2DAT_BITMASK ((0xFF))
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/** Idle data value will be send out in slave mode in case of the actual
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* expecting data requested from the master is greater than its sending data
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* length that can be supported */
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#define I2C_I2DAT_IDLE_CHAR (0xFF)
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/********************************************************************//**
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* I2C Monitor mode control register description
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*********************************************************************/
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#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
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#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
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#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
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#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
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/********************************************************************//**
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* I2C Data buffer register description
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*********************************************************************/
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/** I2C Data buffer register bit mask */
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#define I2DATA_BUFFER_BITMASK ((0xFF))
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/********************************************************************//**
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* I2C Slave Address registers definition
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*********************************************************************/
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/** General Call enable bit */
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#define I2C_I2ADR_GC ((1<<0))
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/** I2C Slave Address registers bit mask */
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#define I2C_I2ADR_BITMASK ((0xFF))
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/********************************************************************//**
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* I2C Mask Register definition
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*********************************************************************/
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/** I2C Mask Register mask field */
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#define I2C_I2MASK_MASK(n) ((n&0xFE))
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/********************************************************************//**
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* I2C SCL HIGH duty cycle Register definition
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*********************************************************************/
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/** I2C SCL HIGH duty cycle Register bit mask */
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#define I2C_I2SCLH_BITMASK ((0xFFFF))
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/********************************************************************//**
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* I2C SCL LOW duty cycle Register definition
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*********************************************************************/
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/** I2C SCL LOW duty cycle Register bit mask */
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#define I2C_I2SCLL_BITMASK ((0xFFFF))
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Public Types --------------------------------------------------------------- */
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/** @defgroup I2C_Public_Types
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* @{
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*/
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/** @brief I2C Own slave address setting structure */
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typedef struct {
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uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
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should be in range from 0..3
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*/
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uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
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uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
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when I2C control being in Slave mode, should be:
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- ENABLE: Enable General Call function.
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- DISABLE: Disable General Call function.
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*/
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uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
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which is set to '1' will cause an automatic compare on
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the corresponding bit of the received address when it
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is compared to the SlaveAddr_7bit value associated with this
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mask register. In other words, bits in SlaveAddr_7bit value
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which are masked are not taken into account in determining
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an address match
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*/
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} I2C_OWNSLAVEADDR_CFG_Type;
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/** @brief Master transfer setup data structure definitions */
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typedef struct
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{
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uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
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uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
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is not used */
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uint32_t tx_length; /**< Transmit data length - 0 if data transmit
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is not used*/
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uint32_t tx_count; /**< Current Transmit data counter */
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uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
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is not used */
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uint32_t rx_length; /**< Receive data length - 0 if data receive is
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not used */
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uint32_t rx_count; /**< Current Receive data counter */
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uint32_t retransmissions_max; /**< Max Re-Transmission value */
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uint32_t retransmissions_count; /**< Current Re-Transmission counter */
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uint32_t status; /**< Current status of I2C activity */
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void (*callback)(void); /**< Pointer to Call back function when transmission complete
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used in interrupt transfer mode */
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} I2C_M_SETUP_Type;
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/** @brief Slave transfer setup data structure definitions */
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typedef struct
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{
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uint8_t* tx_data;
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uint32_t tx_length;
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uint32_t tx_count;
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uint8_t* rx_data;
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uint32_t rx_length;
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uint32_t rx_count;
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uint32_t status;
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void (*callback)(void);
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} I2C_S_SETUP_Type;
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/**
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* @brief Transfer option type definitions
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*/
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typedef enum {
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I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
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I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
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} I2C_TRANSFER_OPT_Type;
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/**
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* @}
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*/
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup I2C_Public_Macros
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* @{
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*/
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#define PARAM_I2C_SLAVEADDR_CH(n) ((n>=0) && (n<=3))
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/** Macro to determine if it is valid SSP port number */
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#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
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|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)) \
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|| (((uint32_t *)n)==((uint32_t *)LPC_I2C2)))
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/* I2C status values */
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#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
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#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
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#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
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/*********************************************************************//**
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* I2C monitor control configuration defines
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**********************************************************************/
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#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
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#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
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#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @defgroup I2C_Public_Functions
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* @{
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*/
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void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock);
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void I2C_DeInit(LPC_I2C_TypeDef* I2Cx);
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void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate);
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void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, FunctionalState NewState);
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Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \
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I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
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Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \
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I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
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void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
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uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx);
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void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
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void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState);
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uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx);
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void I2C0_StdIntHandler(void);
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void I2C1_StdIntHandler(void);
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void I2C2_StdIntHandler(void);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* LPC17XX_I2C_H_ */
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/**
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* @}
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*/
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/* --------------------------------- End Of File ------------------------------ */
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