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/**
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******************************************************************************
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* @file stm32f4xx_fsmc.c
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* @author MCD Application Team
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* @version V1.0.0RC1
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* @date 25-August-2011
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* @brief This file provides firmware functions to manage the following
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* functionalities of the FSMC peripheral:
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* - Interface with SRAM, PSRAM, NOR and OneNAND memories
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* - Interface with NAND memories
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* - Interface with 16-bit PC Card compatible memories
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* - Interrupts and flags management
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*
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_fsmc.h"
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#include "stm32f4xx_rcc.h"
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup FSMC
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* @brief FSMC driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* --------------------- FSMC registers bit mask ---------------------------- */
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/* FSMC BCRx Mask */
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#define BCR_MBKEN_SET ((uint32_t)0x00000001)
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#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
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#define BCR_FACCEN_SET ((uint32_t)0x00000040)
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/* FSMC PCRx Mask */
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#define PCR_PBKEN_SET ((uint32_t)0x00000004)
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#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
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#define PCR_ECCEN_SET ((uint32_t)0x00000040)
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#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
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#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup FSMC_Private_Functions
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* @{
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*/
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/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
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* @brief NOR/SRAM Controller functions
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*
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@verbatim
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===============================================================================
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NOR/SRAM Controller functions
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===============================================================================
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The following sequence should be followed to configure the FSMC to interface with
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SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
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1. Enable the clock for the FSMC and associated GPIOs using the following functions:
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RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
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2. FSMC pins configuration
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- Connect the involved FSMC pins to AF12 using the following function
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GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
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- Configure these FSMC pins in alternate function mode by calling the function
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GPIO_Init();
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3. Declare a FSMC_NORSRAMInitTypeDef structure, for example:
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FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
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the structure member.
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4. Initialize the NOR/SRAM Controller by calling the function
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FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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5. Then enable the NOR/SRAM Bank, for example:
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FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
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6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
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* reset values.
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* @param FSMC_Bank: specifies the FSMC Bank to be used
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* This parameter can be one of the following values:
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* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
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* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
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* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
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* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
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* @retval None
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*/
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void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
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{
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/* Check the parameter */
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assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
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/* FSMC_Bank1_NORSRAM1 */
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if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
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{
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FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
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}
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/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
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else
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{
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FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
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}
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FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
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FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
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}
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/**
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* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
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* parameters in the FSMC_NORSRAMInitStruct.
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* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
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* that contains the configuration information for the FSMC NOR/SRAM
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* specified Banks.
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* @retval None
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*/
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void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
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{
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/* Check the parameters */
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assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
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assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
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assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
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assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
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assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
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assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
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assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
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assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
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assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
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assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
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assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
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assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
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assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
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assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
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assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
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assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
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assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
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assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
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assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
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assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
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/* Bank1 NOR/SRAM control register configuration */
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FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
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(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
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FSMC_NORSRAMInitStruct->FSMC_MemoryType |
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FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
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FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
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FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
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FSMC_NORSRAMInitStruct->FSMC_WrapMode |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
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FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
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FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
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FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
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if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
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{
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FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
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}
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/* Bank1 NOR/SRAM timing register configuration */
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FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
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(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
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/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
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if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
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{
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assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
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assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
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assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
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assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
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assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
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assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
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FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
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(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
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}
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else
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{
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FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
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}
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}
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/**
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* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
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* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure
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* which will be initialized.
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* @retval None
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*/
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void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
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{
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/* Reset NOR/SRAM Init structure parameters values */
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FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
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FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
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FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
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FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
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FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
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FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
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}
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/**
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* @brief Enables or disables the specified NOR/SRAM Memory Bank.
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* @param FSMC_Bank: specifies the FSMC Bank to be used
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* This parameter can be one of the following values:
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* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
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* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
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* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
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* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
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* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
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{
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assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
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FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
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}
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else
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{
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/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
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FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
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}
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}
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/**
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* @}
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*/
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/** @defgroup FSMC_Group2 NAND Controller functions
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* @brief NAND Controller functions
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*
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@verbatim
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===============================================================================
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NAND Controller functions
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===============================================================================
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The following sequence should be followed to configure the FSMC to interface with
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8-bit or 16-bit NAND memory connected to the NAND Bank:
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1. Enable the clock for the FSMC and associated GPIOs using the following functions:
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RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
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2. FSMC pins configuration
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- Connect the involved FSMC pins to AF12 using the following function
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GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
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- Configure these FSMC pins in alternate function mode by calling the function
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|
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GPIO_Init();
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3. Declare a FSMC_NANDInitTypeDef structure, for example:
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|
|
FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
|
|
|
and fill the FSMC_NANDInitStructure variable with the allowed values of
|
|
|
the structure member.
|
|
|
|
|
|
4. Initialize the NAND Controller by calling the function
|
|
|
FSMC_NANDInit(&FSMC_NANDInitStructure);
|
|
|
|
|
|
5. Then enable the NAND Bank, for example:
|
|
|
FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);
|
|
|
|
|
|
6. At this stage you can read/write from/to the memory connected to the NAND Bank.
|
|
|
|
|
|
@note To enable the Error Correction Code (ECC), you have to use the function
|
|
|
FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);
|
|
|
and to get the current ECC value you have to use the function
|
|
|
ECCval = FSMC_GetECC(FSMC_Bank3_NAND);
|
|
|
|
|
|
@endverbatim
|
|
|
* @{
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
|
|
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
|
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
|
|
|
{
|
|
|
/* Check the parameter */
|
|
|
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
|
|
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
/* Set the FSMC_Bank2 registers to their reset values */
|
|
|
FSMC_Bank2->PCR2 = 0x00000018;
|
|
|
FSMC_Bank2->SR2 = 0x00000040;
|
|
|
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
|
|
|
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
|
|
|
}
|
|
|
/* FSMC_Bank3_NAND */
|
|
|
else
|
|
|
{
|
|
|
/* Set the FSMC_Bank3 registers to their reset values */
|
|
|
FSMC_Bank3->PCR3 = 0x00000018;
|
|
|
FSMC_Bank3->SR3 = 0x00000040;
|
|
|
FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
|
|
|
FSMC_Bank3->PATT3 = 0xFCFCFCFC;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Initializes the FSMC NAND Banks according to the specified parameters
|
|
|
* in the FSMC_NANDInitStruct.
|
|
|
* @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that
|
|
|
* contains the configuration information for the FSMC NAND specified Banks.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
|
|
{
|
|
|
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
|
|
|
assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
|
|
|
assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
|
|
|
assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
|
|
|
assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
|
|
|
assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
|
|
|
assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
|
|
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
|
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
|
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
|
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
|
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
|
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
|
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
|
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
|
|
|
|
|
/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
|
|
|
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
|
|
|
PCR_MEMORYTYPE_NAND |
|
|
|
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
|
|
|
FSMC_NANDInitStruct->FSMC_ECC |
|
|
|
FSMC_NANDInitStruct->FSMC_ECCPageSize |
|
|
|
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
|
|
|
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
|
|
|
|
|
|
/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
|
|
|
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
|
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
|
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
|
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
|
|
|
|
|
/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
|
|
|
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
|
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
|
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
|
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
|
|
|
|
|
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
/* FSMC_Bank2_NAND registers configuration */
|
|
|
FSMC_Bank2->PCR2 = tmppcr;
|
|
|
FSMC_Bank2->PMEM2 = tmppmem;
|
|
|
FSMC_Bank2->PATT2 = tmppatt;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* FSMC_Bank3_NAND registers configuration */
|
|
|
FSMC_Bank3->PCR3 = tmppcr;
|
|
|
FSMC_Bank3->PMEM3 = tmppmem;
|
|
|
FSMC_Bank3->PATT3 = tmppatt;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
|
|
|
/**
|
|
|
* @brief Fills each FSMC_NANDInitStruct member with its default value.
|
|
|
* @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which
|
|
|
* will be initialized.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
|
|
{
|
|
|
/* Reset NAND Init structure parameters values */
|
|
|
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
|
|
|
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
|
|
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
|
|
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
|
|
|
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
|
|
|
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
|
|
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
|
|
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
|
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
|
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
|
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
|
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
|
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
|
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
|
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Enables or disables the specified NAND Memory Bank.
|
|
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
|
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
|
|
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
|
|
{
|
|
|
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
{
|
|
|
/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/**
|
|
|
* @brief Enables or disables the FSMC NAND ECC feature.
|
|
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
|
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
|
|
* @param NewState: new state of the FSMC NAND ECC feature.
|
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
|
|
{
|
|
|
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
{
|
|
|
/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Returns the error correction code register value.
|
|
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
|
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
|
|
* @retval The Error Correction Code (ECC) value.
|
|
|
*/
|
|
|
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
|
|
|
{
|
|
|
uint32_t eccval = 0x00000000;
|
|
|
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
/* Get the ECCR2 register value */
|
|
|
eccval = FSMC_Bank2->ECCR2;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Get the ECCR3 register value */
|
|
|
eccval = FSMC_Bank3->ECCR3;
|
|
|
}
|
|
|
/* Return the error correction code value */
|
|
|
return(eccval);
|
|
|
}
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/** @defgroup FSMC_Group3 PCCARD Controller functions
|
|
|
* @brief PCCARD Controller functions
|
|
|
*
|
|
|
@verbatim
|
|
|
===============================================================================
|
|
|
PCCARD Controller functions
|
|
|
===============================================================================
|
|
|
|
|
|
The following sequence should be followed to configure the FSMC to interface with
|
|
|
16-bit PC Card compatible memory connected to the PCCARD Bank:
|
|
|
|
|
|
1. Enable the clock for the FSMC and associated GPIOs using the following functions:
|
|
|
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
|
|
|
|
|
|
2. FSMC pins configuration
|
|
|
- Connect the involved FSMC pins to AF12 using the following function
|
|
|
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
|
|
|
- Configure these FSMC pins in alternate function mode by calling the function
|
|
|
GPIO_Init();
|
|
|
|
|
|
3. Declare a FSMC_PCCARDInitTypeDef structure, for example:
|
|
|
FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure;
|
|
|
and fill the FSMC_PCCARDInitStructure variable with the allowed values of
|
|
|
the structure member.
|
|
|
|
|
|
4. Initialize the PCCARD Controller by calling the function
|
|
|
FSMC_PCCARDInit(&FSMC_PCCARDInitStructure);
|
|
|
|
|
|
5. Then enable the PCCARD Bank:
|
|
|
FSMC_PCCARDCmd(ENABLE);
|
|
|
|
|
|
6. At this stage you can read/write from/to the memory connected to the PCCARD Bank.
|
|
|
|
|
|
@endverbatim
|
|
|
* @{
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_PCCARDDeInit(void)
|
|
|
{
|
|
|
/* Set the FSMC_Bank4 registers to their reset values */
|
|
|
FSMC_Bank4->PCR4 = 0x00000018;
|
|
|
FSMC_Bank4->SR4 = 0x00000000;
|
|
|
FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
|
|
|
FSMC_Bank4->PATT4 = 0xFCFCFCFC;
|
|
|
FSMC_Bank4->PIO4 = 0xFCFCFCFC;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Initializes the FSMC PCCARD Bank according to the specified parameters
|
|
|
* in the FSMC_PCCARDInitStruct.
|
|
|
* @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure
|
|
|
* that contains the configuration information for the FSMC PCCARD Bank.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
|
|
|
assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
|
|
|
assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
|
|
|
|
|
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
|
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
|
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
|
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
|
|
|
|
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
|
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
|
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
|
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
|
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
|
|
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
|
|
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
|
|
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
|
|
|
|
|
|
/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
|
|
|
FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
|
|
|
FSMC_MemoryDataWidth_16b |
|
|
|
(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
|
|
|
(FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
|
|
|
|
|
|
/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
|
|
|
FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
|
|
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
|
|
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
|
|
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
|
|
|
|
|
/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
|
|
|
FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
|
|
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
|
|
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
|
|
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
|
|
|
|
|
/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
|
|
|
FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
|
|
|
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
|
|
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
|
|
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Fills each FSMC_PCCARDInitStruct member with its default value.
|
|
|
* @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure
|
|
|
* which will be initialized.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
|
|
{
|
|
|
/* Reset PCCARD Init structure parameters values */
|
|
|
FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
|
|
FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
|
|
FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
|
|
|
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
|
|
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Enables or disables the PCCARD Memory Bank.
|
|
|
* @param NewState: new state of the PCCARD Memory Bank.
|
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_PCCARDCmd(FunctionalState NewState)
|
|
|
{
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
{
|
|
|
/* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
|
|
|
FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
|
|
|
FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
|
|
|
}
|
|
|
}
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/** @defgroup FSMC_Group4 Interrupts and flags management functions
|
|
|
* @brief Interrupts and flags management functions
|
|
|
*
|
|
|
@verbatim
|
|
|
===============================================================================
|
|
|
Interrupts and flags management functions
|
|
|
===============================================================================
|
|
|
|
|
|
@endverbatim
|
|
|
* @{
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @brief Enables or disables the specified FSMC interrupts.
|
|
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
|
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
|
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
|
|
* @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
|
|
|
* This parameter can be any combination of the following values:
|
|
|
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
|
|
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
|
|
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
|
|
* @param NewState: new state of the specified FSMC interrupts.
|
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
|
|
|
{
|
|
|
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
|
|
assert_param(IS_FSMC_IT(FSMC_IT));
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
{
|
|
|
/* Enable the selected FSMC_Bank2 interrupts */
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
FSMC_Bank2->SR2 |= FSMC_IT;
|
|
|
}
|
|
|
/* Enable the selected FSMC_Bank3 interrupts */
|
|
|
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
|
|
{
|
|
|
FSMC_Bank3->SR3 |= FSMC_IT;
|
|
|
}
|
|
|
/* Enable the selected FSMC_Bank4 interrupts */
|
|
|
else
|
|
|
{
|
|
|
FSMC_Bank4->SR4 |= FSMC_IT;
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the selected FSMC_Bank2 interrupts */
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
|
|
|
FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
|
|
|
}
|
|
|
/* Disable the selected FSMC_Bank3 interrupts */
|
|
|
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
|
|
{
|
|
|
FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
|
|
|
}
|
|
|
/* Disable the selected FSMC_Bank4 interrupts */
|
|
|
else
|
|
|
{
|
|
|
FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Checks whether the specified FSMC flag is set or not.
|
|
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
|
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
|
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
|
|
* @param FSMC_FLAG: specifies the flag to check.
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
|
|
|
* @arg FSMC_FLAG_Level: Level detection Flag.
|
|
|
* @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
|
|
|
* @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
|
|
|
* @retval The new state of FSMC_FLAG (SET or RESET).
|
|
|
*/
|
|
|
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
|
|
{
|
|
|
FlagStatus bitstatus = RESET;
|
|
|
uint32_t tmpsr = 0x00000000;
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
|
|
assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
|
|
|
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
tmpsr = FSMC_Bank2->SR2;
|
|
|
}
|
|
|
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
|
|
{
|
|
|
tmpsr = FSMC_Bank3->SR3;
|
|
|
}
|
|
|
/* FSMC_Bank4_PCCARD*/
|
|
|
else
|
|
|
{
|
|
|
tmpsr = FSMC_Bank4->SR4;
|
|
|
}
|
|
|
|
|
|
/* Get the flag status */
|
|
|
if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
|
|
|
{
|
|
|
bitstatus = SET;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
bitstatus = RESET;
|
|
|
}
|
|
|
/* Return the flag status */
|
|
|
return bitstatus;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Clears the FSMC's pending flags.
|
|
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
|
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
|
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
|
|
* @param FSMC_FLAG: specifies the flag to clear.
|
|
|
* This parameter can be any combination of the following values:
|
|
|
* @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
|
|
|
* @arg FSMC_FLAG_Level: Level detection Flag.
|
|
|
* @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
|
|
assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
|
|
|
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
FSMC_Bank2->SR2 &= ~FSMC_FLAG;
|
|
|
}
|
|
|
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
|
|
{
|
|
|
FSMC_Bank3->SR3 &= ~FSMC_FLAG;
|
|
|
}
|
|
|
/* FSMC_Bank4_PCCARD*/
|
|
|
else
|
|
|
{
|
|
|
FSMC_Bank4->SR4 &= ~FSMC_FLAG;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Checks whether the specified FSMC interrupt has occurred or not.
|
|
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
|
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
|
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
|
|
* @param FSMC_IT: specifies the FSMC interrupt source to check.
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
|
|
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
|
|
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
|
|
* @retval The new state of FSMC_IT (SET or RESET).
|
|
|
*/
|
|
|
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
|
|
{
|
|
|
ITStatus bitstatus = RESET;
|
|
|
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
|
|
assert_param(IS_FSMC_GET_IT(FSMC_IT));
|
|
|
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
tmpsr = FSMC_Bank2->SR2;
|
|
|
}
|
|
|
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
|
|
{
|
|
|
tmpsr = FSMC_Bank3->SR3;
|
|
|
}
|
|
|
/* FSMC_Bank4_PCCARD*/
|
|
|
else
|
|
|
{
|
|
|
tmpsr = FSMC_Bank4->SR4;
|
|
|
}
|
|
|
|
|
|
itstatus = tmpsr & FSMC_IT;
|
|
|
|
|
|
itenable = tmpsr & (FSMC_IT >> 3);
|
|
|
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
|
|
|
{
|
|
|
bitstatus = SET;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
bitstatus = RESET;
|
|
|
}
|
|
|
return bitstatus;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Clears the FSMC's interrupt pending bits.
|
|
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
|
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
|
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
|
|
* @param FSMC_IT: specifies the interrupt pending bit to clear.
|
|
|
* This parameter can be any combination of the following values:
|
|
|
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
|
|
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
|
|
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
|
|
assert_param(IS_FSMC_IT(FSMC_IT));
|
|
|
|
|
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
|
|
{
|
|
|
FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
|
|
|
}
|
|
|
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
|
|
{
|
|
|
FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
|
|
|
}
|
|
|
/* FSMC_Bank4_PCCARD*/
|
|
|
else
|
|
|
{
|
|
|
FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
|
|
|
