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simulator.pro
14 lines | 264 B | text/idl | PrologLexer
contains(UCMODEL,simulator)
{
TEMPLATE = subdirs
CONFIG += ordered
SUBDIRS = CORE/core.pro \
CPU/cpu.pro \
GPIO/gpio.pro \
UART/uart.pro \
SPI/spi.pro \
I2C/i2c.pro \
SDCARD \
SDLCD
}