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/*------------------------------------------------------------------------------
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-- This file is a part of the libuc, microcontroler library
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-- Copyright (C) 2011, Alexis Jeandet
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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-------------------------------------------------------------------------------*/
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#include <uart.h>
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#include <stm32f4xx_rcc.h>
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#include <stm32f4xx_gpio.h>
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#include <gpio.h>
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#include <stdio.h>
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#define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
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#define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
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USART_TypeDef* _uart_dev_table[6]={USART1,USART2,USART3,UART4,UART5,USART6};
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int _uartstrsetpos(streamdevice* device,int pos);
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int _uartstrread(streamdevice* device,void* data,int size, int n);
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int _uartstrwrite(streamdevice* device,void* data,int size, int n);
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streamdevice_ops UART_OPS=
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{
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.write = &_uartstrwrite,
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.read = &_uartstrread,
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.setpos= &_uartstrsetpos,
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.close = NULL
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};
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uart_t uartopen(int count)
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{
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switch(count)
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{
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case uart1:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
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USART1->CR3 &= ~((1<<8) + (1<<9));
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return uart1;
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break;
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case uart2:
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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USART2->CR3 &= ~((1<<8) + (1<<9));
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return uart2;
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break;
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case uart3:
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
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USART3->CR3 &= ~((1<<8) + (1<<9));
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return uart3;
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break;
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case uart4:
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
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UART4->CR3 &= ~((1<<8) + (1<<9));
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return uart4;
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break;
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case uart5:
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
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return uart5;
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break;
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case uart6:
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
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return uart6;
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break;
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default:
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break;
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}
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return -1;
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}
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uart_t uartopenandconfig(int count, uint32_t cfg, uint32_t speed, uint32_t TXpin, uint32_t RXpin, uint32_t RTSpin, uint32_t CTSpin)
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{
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uart_t dev= uartopen(count);
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uartsetconfig(dev,cfg,speed);
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uartsetpins(dev,TXpin,RXpin,RTSpin,CTSpin);
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return dev;
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}
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int uartclose(uart_t uart)
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{
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switch(uart)
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{
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case uart1:
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
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break;
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case uart2:
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
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break;
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case uart3:
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
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break;
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case uart4:
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
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break;
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case uart5:
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
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break;
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case uart6:
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
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break;
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default:
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return -1;
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break;
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}
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return 1;
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}
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int uartsetpins(uart_t uart,uint32_t TXpin,uint32_t RXpin,uint32_t RTSpin,uint32_t CTSpin)
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{
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if(uart >5)return -1;
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if(uart <0)return -1;
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gpio_t TX,RX,CTS,RTS;
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TX = gpioopen(TXpin);
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RX = gpioopen(RXpin);
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TX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
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RX |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
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gpiosetconfig(&TX);
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gpiosetconfig(&RX);
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uint8_t gpioAFuartx = GPIO_AF_USART1;
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switch(uart)
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{
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case uart1:
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gpioAFuartx = GPIO_AF_USART1;
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break;
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case uart2:
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gpioAFuartx = GPIO_AF_USART2;
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break;
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case uart3:
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gpioAFuartx = GPIO_AF_USART3;
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break;
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case uart4:
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gpioAFuartx = GPIO_AF_UART4;
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break;
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case uart5:
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gpioAFuartx = GPIO_AF_UART5;
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break;
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case uart6:
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gpioAFuartx = GPIO_AF_USART6;
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break;
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default:
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return -1;
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break;
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}
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GPIO_PinAFConfig(GPIOGETPORT(TX), (uint8_t)(TX & 0xF), gpioAFuartx);
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GPIO_PinAFConfig(GPIOGETPORT(RX), (uint8_t)(RX & 0xF), gpioAFuartx);
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if((gpioAFuartx!=GPIO_AF_UART5) && (gpioAFuartx!=GPIO_AF_UART4))
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{
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if(CTSpin!=-1)
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{
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CTS = gpioopen(CTSpin);
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CTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
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gpiosetconfig(&CTS);
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GPIO_PinAFConfig(GPIOGETPORT(CTS), (uint8_t)(CTS & 0xF), gpioAFuartx);
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}
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if(RTSpin!=-1)
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{
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RTS = gpioopen(RTSpin);
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RTS |= gpiolowspeed | gpioaf | gpiopushpulltype | gpionopulltype;
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gpiosetconfig(&RTS);
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GPIO_PinAFConfig(GPIOGETPORT(RTS), (uint8_t)(RTS & 0xF), gpioAFuartx);
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}
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}
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return 1;
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}
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int uartsetconfig(uart_t uart, uint32_t cfg, uint32_t speed)
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{
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int res=1;
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uartdisable(uart);
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uartsetspeed(uart,speed);
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uartsetparity(uart,cfg & UARTPARITYMASK);
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uartsetdatabits(uart,cfg & UARTBITSMASK);
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uartsetstopbits(uart,cfg & UARTSTOPBITSMASK);
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uartenable(uart);
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return res;
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}
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int uartenable(uart_t uart)
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{
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if((uart<6)&&(uart>=0))
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{
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USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
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_dev_->CR1 |= (1<<13);
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_dev_->CR1 |= (1<<2) + (1<<3);
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_dev_->DR = ' ';
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return 1;
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}
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return -1;
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}
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int uartdisable(uart_t uart)
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{
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if((uart<6)&&(uart>=0))
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{
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USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
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if((_dev_->CR1 & ((1<<3) +(1<<13)))==((1<<3) +(1<<13)))
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{
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while((_dev_->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
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}
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_dev_->CR1 &= ~((1<<2) + (1<<3) +(1<<13));
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return 1;
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}
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return -1;
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}
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int uartsetspeed(uart_t uart,uint32_t speed)
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{
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if((uart<6)&&(uart>=0))
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{
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USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
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uint32_t tmpreg = 0x00, apbclock = 0x00;
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uint32_t integerdivider = 0x00;
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uint32_t fractionaldivider = 0x00;
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RCC_ClocksTypeDef RCC_ClocksStatus;
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RCC_GetClocksFreq(&RCC_ClocksStatus);
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if ((_dev_ == USART1) || ((_dev_ == USART6)))
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{
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apbclock = RCC_ClocksStatus.PCLK2_Frequency;
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}
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else
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{
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apbclock = RCC_ClocksStatus.PCLK1_Frequency;
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}
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if (((_dev_->CR1) & USART_CR1_OVER8) != (uint16_t)0)
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{
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integerdivider = ((25 * apbclock) / (2 * (speed)));
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}
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else
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{
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integerdivider = ((25 * apbclock) / (4 * (speed)));
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}
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tmpreg = (integerdivider / 100) << 4;
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fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
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if ((_dev_->CR1 & USART_CR1_OVER8) != (uint16_t)0)
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{
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tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
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}
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else
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{
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tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
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}
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_dev_->BRR = (uint16_t)tmpreg;
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return 1;
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}
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return -1;
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}
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int uartsetparity(uart_t uart,uartparity_t parity)
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{
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if((uart<6)&&(uart>=0))
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{
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USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
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_dev_->CR1 &= ~(((1<<9)+(1<<10)));
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switch(parity)
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{
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case uartparityeven:
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_dev_->CR1 |= (1<<10);
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break;
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case uartparityodd:
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_dev_->CR1 |= (1<<10) + (1<<9);
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break;
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case uartparitynone:
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break;
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default :
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return 0;
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break;
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}
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return 1;
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}
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return -1;
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}
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int uartsetdatabits(uart_t uart,uartbits_t databits)
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{
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if((uart<6)&&(uart>=0))
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{
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USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
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_dev_->CR1 &= ~(((1<<12)));
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switch(databits)
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{
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case uart7bits:
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return 0;
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break;
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case uart8bits:
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break;
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case uart9bits:
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_dev_->CR1 |= (1<<12);
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break;
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default :
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return 0;
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break;
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}
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return 1;
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}
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return -1;
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}
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int uartsetstopbits(uart_t uart,uartstopbits_t stopbits)
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{
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if((uart<6)&&(uart>=0))
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{
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USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
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_dev_->CR2 &= ~(((1<<12)+(1<<13)));
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switch(stopbits)
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{
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case uarthalfstop:
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_dev_->CR2 |= (1<<12);
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break;
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case uartonestop:
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break;
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case uartonehalfstop:
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_dev_->CR2 |= (1<<12) + (1<<13);
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break;
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case uarttwostop:
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_dev_->CR2 |= (1<<13);
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break;
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default :
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return 0;
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break;
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}
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return 1;
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}
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return -1;
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}
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int uartputc(uart_t uart,char c)
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{
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if((uart<6)&&(uart>=0))
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{
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USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
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while((_dev_->SR & (uint16_t)(1<<7))!=(uint16_t)(1<<7));
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_dev_->DR = c;
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return 1;
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}
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return -1;
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}
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char uartgetc(uart_t uart)
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{
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if((uart<6)&&(uart>=0))
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{
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USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
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while(!(_dev_->SR & (1<<5)));
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return (char)_dev_->DR;
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}
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return -1;
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}
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int uartputs(uart_t uart,char* s)
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{
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while (*s) uartputc(uart,*s++);
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return 1;
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}
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int uartgets(uart_t uart,char* s)
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{
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do
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{
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(*s) = uartgetc(uart);
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}
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while(*s++);
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return 1;
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}
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int uartputnc(uart_t uart,char* c,int n)
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{
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int l=0;
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while(l<n)
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{
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uartputc(uart,*c++);
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l++;
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}
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return n;
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}
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int uartgetnc(uart_t uart,char* c,int n)
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{
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int l=0;
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while(l<n)
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{
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*c++=uartgetc(uart);
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l++;
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}
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return n;
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}
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int uartavailiabledata(uart_t uart)
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{
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if((uart<6)&&(uart>=0))
|
|
|
{
|
|
|
USART_TypeDef* _dev_ = _uart_dev_table[(int)uart];
|
|
|
if(!(_dev_->SR & (1<<5)))
|
|
|
return 0;
|
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|
else
|
|
|
return 1;
|
|
|
}
|
|
|
return -1;
|
|
|
}
|
|
|
|
|
|
|
|
|
int _uartstrwrite(streamdevice* device,void* data,int size, int n)
|
|
|
{
|
|
|
return uartputnc((uart_t) device->_stream,(char*) data,size*n);
|
|
|
}
|
|
|
|
|
|
int _uartstrread(streamdevice* device,void* data,int size, int n)
|
|
|
{
|
|
|
return uartgetnc((uart_t) device->_stream,(char*) data,size*n);
|
|
|
}
|
|
|
|
|
|
int _uartstrsetpos(streamdevice* device,int pos)
|
|
|
{
|
|
|
return 1;
|
|
|
}
|
|
|
|
|
|
int uartmkstreamdev(uart_t uart,streamdevice* strdev)
|
|
|
{
|
|
|
strdev->_stream = (UHANDLE)uart;/*
|
|
|
strdev->write = (write_t)&_uartstrwrite;
|
|
|
strdev->read = (read_t)&_uartstrread;
|
|
|
strdev->setpos = (setpos_t)&_uartstrsetpos;*/
|
|
|
strdev->ops = &UART_OPS;
|
|
|
strdev->streamPt = 0;
|
|
|
return 1;
|
|
|
}
|
|
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