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/*------------------------------------------------------------------------------
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-- This file is a part of the libuc, microcontroler library
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-- Copyright (C) 2012, Alexis Jeandet
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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-------------------------------------------------------------------------------*/
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#include <dma.h>
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#include <stm32f4xx_gpio.h>
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#include <stm32f4xx_rcc.h>
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#include <stm32f4xx_dma.h>
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#include <misc.h>
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#define GPIOGETPORT(gpio) ((GPIO_TypeDef*)(((((uint32_t)gpio) & (uint32_t)0x0000FF00)*(uint32_t)4) + (uint32_t)GPIOA))
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#define GPIOPORTNUM(gpio) (((uint32_t)(gpio) & (uint32_t)0x0000FF00)>>(uint32_t)8)
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typedef enum dmaStreamState
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{
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avail=0,
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inUse=1,
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locked=2,
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}dmaStreamState;
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char __DMA2_streams__[8]={avail,avail,avail,avail,avail,avail,avail,avail};
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DMA_Stream_TypeDef* __DMA2_streams_list__[8]={DMA2_Stream0,DMA2_Stream1,DMA2_Stream2,DMA2_Stream3,DMA2_Stream4,DMA2_Stream5,DMA2_Stream6,DMA2_Stream7};
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int __DMA2_streams_channels__[8]={DMA_Channel_1,DMA_Channel_3,DMA_Channel_2,DMA_Channel_0,DMA_Channel_3,DMA_Channel_5,DMA_Channel_3,DMA_Channel_3};
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uint32_t __DMA2_streams_remainig_data__[8]={0,0,0,0,0,0,0,0};
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int __DMA_Csts__[8]={0,0,0,0,0,0,0,0};
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char __dma_is_initialised =0;
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typedef struct _dma_config_
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{
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uint32_t source;
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uint32_t dest;
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int size;
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int count;
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char incSrc;
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char incDest;
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}_dma_config_;
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_dma_config_ __DMA2_streams_config__[8];
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void __set_DMA_inc__(DMA_InitTypeDef* DMA_InitStructure,int* incsz,int*datacnt)
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{
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switch (*incsz) {
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case 1:
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DMA_InitStructure->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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break;
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case 2:
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DMA_InitStructure->DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure->DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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break;
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case 4:
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DMA_InitStructure->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
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DMA_InitStructure->DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
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break;
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default:
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DMA_InitStructure->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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(*datacnt)*=(*incsz);
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*incsz=1;
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break;
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}
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}
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void __DMA2_init()
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{
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int irq[8]={DMA2_Stream0_IRQn,DMA2_Stream1_IRQn,DMA2_Stream2_IRQn,DMA2_Stream3_IRQn,DMA2_Stream4_IRQn,DMA2_Stream5_IRQn,DMA2_Stream6_IRQn,DMA2_Stream7_IRQn};
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NVIC_InitTypeDef NVIC_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
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for(int i=0;i<8;i++)
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{
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if(__DMA2_streams__[i]!=locked)
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{
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DMA_DeInit(__DMA2_streams_list__[i]);
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DMA_ITConfig(__DMA2_streams_list__[i], DMA_IT_TC, ENABLE);
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NVIC_InitStructure.NVIC_IRQChannel = irq[i];
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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}
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}
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__dma_is_initialised = 1;
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}
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void __dmacopy__(uint32_t source, uint32_t dest, int size, int count,char incSrc,char incDest,int streamIndex)
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{
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DMA_InitTypeDef DMA_InitStructure;
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DMA_Stream_TypeDef* stream=__DMA2_streams_list__[streamIndex];
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while (DMA_GetCmdStatus(stream) != DISABLE);
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__set_DMA_inc__(&DMA_InitStructure,&size,&count);
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DMA_InitStructure.DMA_Channel = __DMA2_streams_channels__[streamIndex];
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DMA_InitStructure.DMA_PeripheralBaseAddr = source;
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DMA_InitStructure.DMA_Memory0BaseAddr = dest;
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToMemory;
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if(count>65535)
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{
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DMA_InitStructure.DMA_BufferSize = 65535;
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__DMA2_streams_config__[streamIndex].count = count-65535;
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}
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else
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{
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DMA_InitStructure.DMA_BufferSize = count;
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__DMA2_streams_config__[streamIndex].count = 0;
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}
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__DMA2_streams_config__[streamIndex].incDest = incDest;
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__DMA2_streams_config__[streamIndex].incSrc = incSrc;
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__DMA2_streams_config__[streamIndex].size = size;
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if(incSrc)
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{
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__DMA2_streams_config__[streamIndex].source = source+(DMA_InitStructure.DMA_BufferSize*size);
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
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}
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else
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{
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__DMA2_streams_config__[streamIndex].source = source;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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}
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if(incDest)
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{
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__DMA2_streams_config__[streamIndex].dest = dest+(DMA_InitStructure.DMA_BufferSize*size);
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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}
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else
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{
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__DMA2_streams_config__[streamIndex].dest = dest;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
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DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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DMA_Init(stream, &DMA_InitStructure);
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DMA_Cmd(stream, ENABLE);
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}
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dmaID_t dmacopy(uint32_t source, uint32_t dest, int size, int count,char incSrc,char incDest)
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{
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int streamIndex;
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if(!__dma_is_initialised)
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{
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__DMA2_init();
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}
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for(int i=0;i<8;i++)
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{
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if(__DMA2_streams__[i]==avail)
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{
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streamIndex=i;
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__DMA2_streams__[i]=inUse;
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break;
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}
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}
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__dmacopy__(source,dest,size,count,incSrc,incDest,streamIndex);
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return streamIndex;
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}
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void DMA2_continueCp(int streamIndex)
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{
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DMA_InitTypeDef DMA_InitStructure;
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DMA_Stream_TypeDef* stream = __DMA2_streams_list__[streamIndex];
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if ((DMA_GetCmdStatus(stream) != DISABLE) && (__DMA2_streams__[streamIndex]==inUse))
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{
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return;
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}
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if(__DMA2_streams_config__[streamIndex].count==0)
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{
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__DMA2_streams__[streamIndex]=avail;
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return;
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}
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__set_DMA_inc__(&DMA_InitStructure,&(__DMA2_streams_config__[streamIndex].size),&(__DMA2_streams_config__[streamIndex].count));
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DMA_InitStructure.DMA_Channel = __DMA2_streams_channels__[streamIndex];
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToMemory;
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DMA_InitStructure.DMA_PeripheralBaseAddr = __DMA2_streams_config__[streamIndex].source;
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DMA_InitStructure.DMA_Memory0BaseAddr = __DMA2_streams_config__[streamIndex].dest;
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if(__DMA2_streams_config__[streamIndex].count>65535)
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{
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DMA_InitStructure.DMA_BufferSize = 65535;
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__DMA2_streams_config__[streamIndex].count = __DMA2_streams_config__[streamIndex].count-65535;
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}
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else
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{
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DMA_InitStructure.DMA_BufferSize = __DMA2_streams_config__[streamIndex].count;
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__DMA2_streams_config__[streamIndex].count = 0;
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}
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if(__DMA2_streams_config__[streamIndex].incSrc)
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{
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__DMA2_streams_config__[streamIndex].source +=(DMA_InitStructure.DMA_BufferSize*__DMA2_streams_config__[streamIndex].size);
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
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}
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else
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{
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__DMA2_streams_config__[streamIndex].source = __DMA2_streams_config__[streamIndex].source;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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}
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if(__DMA2_streams_config__[streamIndex].incDest)
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{
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__DMA2_streams_config__[streamIndex].dest +=(DMA_InitStructure.DMA_BufferSize*__DMA2_streams_config__[streamIndex].size);
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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}
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else
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{
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__DMA2_streams_config__[streamIndex].dest = __DMA2_streams_config__[streamIndex].dest;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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}
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
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DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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DMA_Init(stream, &DMA_InitStructure);
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DMA_Cmd(stream, ENABLE);
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}
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void DMA2_Stream0_IRQHandler(void)
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{
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if(DMA_GetITStatus(DMA2_Stream0, DMA_IT_TCIF0))
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{
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF0);
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DMA2_continueCp(0);
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}
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}
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void DMA2_Stream1_IRQHandler(void)
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{
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if(DMA_GetITStatus(DMA2_Stream1, DMA_IT_TCIF1))
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{
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream1, DMA_IT_TCIF1);
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DMA2_continueCp(1);
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}
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}
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void DMA2_Stream2_IRQHandler(void)
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{
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if(DMA_GetITStatus(DMA2_Stream2, DMA_IT_TCIF2))
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{
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream2, DMA_IT_TCIF2);
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DMA2_continueCp(2);
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}
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}
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void DMA2_Stream3_IRQHandler(void)
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{
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if(DMA_GetITStatus(DMA2_Stream3, DMA_IT_TCIF3))
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{
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream3, DMA_IT_TCIF3);
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DMA2_continueCp(3);
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}
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}
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void DMA2_Stream4_IRQHandler(void)
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{
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if(DMA_GetITStatus(DMA2_Stream4, DMA_IT_TCIF4))
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{
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream4, DMA_IT_TCIF4);
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DMA2_continueCp(4);
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}
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}
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void DMA2_Stream5_IRQHandler(void)
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{
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if(DMA_GetITStatus(DMA2_Stream5, DMA_IT_TCIF5))
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{
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream5, DMA_IT_TCIF5);
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DMA2_continueCp(5);
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}
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}
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void DMA2_Stream6_IRQHandler(void)
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{
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if(DMA_GetITStatus(DMA2_Stream6, DMA_IT_TCIF6))
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{
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream6, DMA_IT_TCIF6);
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DMA2_continueCp(6);
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}
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}
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void DMA2_Stream7_IRQHandler(void)
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{
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if(DMA_GetITStatus(DMA2_Stream7, DMA_IT_TCIF7))
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{
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream7, DMA_IT_TCIF7);
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DMA2_continueCp(7);
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}
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}
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int dmaIsReady(dmaID_t dmaID)
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{
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if(!__dma_is_initialised)
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{
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__DMA2_init();
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}
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return __DMA2_streams__[dmaID]==avail;
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}
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int dmaLockStream(int stream, int dmaDev)
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{
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if(!__dma_is_initialised)
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{
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__DMA2_init();
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}
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if(dmaDev==2)
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{
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if(__DMA2_streams__[stream]==locked)
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{
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return 0;
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}
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while(__DMA2_streams__[stream]==inUse);
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__DMA2_streams__[stream]=locked;
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return 1;
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}
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}
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dmaID_t dmamemset(uint32_t dest, int val, int size)
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{
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int streamIndex;
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if(!__dma_is_initialised)
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{
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__DMA2_init();
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}
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for(int i=0;i<8;i++)
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{
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if(__DMA2_streams__[i]==avail)
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{
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streamIndex=i;
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__DMA2_streams__[i]=inUse;
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break;
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}
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}
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__DMA_Csts__[streamIndex]=val;
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__dmacopy__((uint32_t)(__DMA_Csts__ + streamIndex),dest,1,size,0,1,streamIndex);
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return streamIndex;
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}
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