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/* File: startup_ARMCM4.S
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* Purpose: startup file for Cortex-M4 devices. Should use with
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* GCC for ARM Embedded Processors
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* Version: V2.0
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* Date: 16 August 2013
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*
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/* Copyright (c) 2011 - 2013 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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/*
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2013 Modified for libuc2 use by Alexis Jeandet.
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*/
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.syntax unified
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.cpu cortex-m4
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.fpu fpv4-sp-d16
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0x7F00
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x7F00
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .isr_vector
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts */
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.word WWDG_IRQHandler /* Window WatchDog */
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.word PVD_IRQHandler /* PVD through EXTI Line detection */
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.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
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.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_IRQHandler /* RCC */
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.word EXTI0_IRQHandler /* EXTI Line0 */
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.word EXTI1_IRQHandler /* EXTI Line1 */
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.word EXTI2_IRQHandler /* EXTI Line2 */
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.word EXTI3_IRQHandler /* EXTI Line3 */
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.word EXTI4_IRQHandler /* EXTI Line4 */
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.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
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.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
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.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
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.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
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.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
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.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
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.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
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.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
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.word CAN1_TX_IRQHandler /* CAN1 TX */
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.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
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.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
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.word CAN1_SCE_IRQHandler /* CAN1 SCE */
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.word EXTI9_5_IRQHandler /* External Line[9:5]s */
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.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
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.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
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.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word TIM3_IRQHandler /* TIM3 */
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.word TIM4_IRQHandler /* TIM4 */
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.word I2C1_EV_IRQHandler /* I2C1 Event */
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.word I2C1_ER_IRQHandler /* I2C1 Error */
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.word I2C2_EV_IRQHandler /* I2C2 Event */
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.word I2C2_ER_IRQHandler /* I2C2 Error */
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.word SPI1_IRQHandler /* SPI1 */
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.word SPI2_IRQHandler /* SPI2 */
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.word USART1_IRQHandler /* USART1 */
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.word USART2_IRQHandler /* USART2 */
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.word USART3_IRQHandler /* USART3 */
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.word EXTI15_10_IRQHandler /* External Line[15:10]s */
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.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
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.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
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.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
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.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
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.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
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.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
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.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
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.word FSMC_IRQHandler /* FSMC */
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.word SDIO_IRQHandler /* SDIO */
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.word TIM5_IRQHandler /* TIM5 */
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.word SPI3_IRQHandler /* SPI3 */
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.word UART4_IRQHandler /* UART4 */
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.word UART5_IRQHandler /* UART5 */
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.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
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.word TIM7_IRQHandler /* TIM7 */
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.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
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.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
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.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
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.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
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.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
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.word ETH_IRQHandler /* Ethernet */
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.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
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.word CAN2_TX_IRQHandler /* CAN2 TX */
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.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
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.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
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.word CAN2_SCE_IRQHandler /* CAN2 SCE */
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.word OTG_FS_IRQHandler /* USB OTG FS */
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.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
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.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
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.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
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.word USART6_IRQHandler /* USART6 */
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.word I2C3_EV_IRQHandler /* I2C3 event */
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.word I2C3_ER_IRQHandler /* I2C3 error */
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.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
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.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
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.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
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.word OTG_HS_IRQHandler /* USB OTG HS */
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.word DCMI_IRQHandler /* DCMI */
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.word CRYP_IRQHandler /* CRYP crypto */
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.word HASH_RNG_IRQHandler /* Hash and Rng */
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.word FPU_IRQHandler /* FPU */
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.size __isr_vector, . - __isr_vector
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.text
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.thumb
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.thumb_func
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.align 2
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Firstly it copies data from read only memory to RAM. There are two schemes
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* to copy. One can copy more than one sections. Another can only copy
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* one section. The former scheme needs more instructions and read-only
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* data to implement than the latter.
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* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
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/* Single section scheme.
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*
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* The ranges of copy from/to are specified by following symbols
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* __etext: LMA of start of the section to copy from. Usually end of text
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* __data_start__: VMA of start of the section to copy to
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* __data_end__: VMA of end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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.L_loop1:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .L_loop1
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* There are two schemes too. One can clear multiple BSS sections. Another
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* can only clear one section. The former is more size expensive than the
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* latter.
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*
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* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
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* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
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*/
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/* Single BSS section scheme.
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*
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* The BSS section is specified by following symbols
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* __bss_start__: start of the BSS section.
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* __bss_end__: end of the BSS section.
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*
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* Both addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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.L_loop3:
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cmp r1, r2
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itt lt
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strlt r0, [r1], #4
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blt .L_loop3
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bl main
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, Default_Handler
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.endm
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler MemManage_Handler
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def_irq_handler BusFault_Handler
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def_irq_handler UsageFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler DebugMon_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler DEF_IRQHandler
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def_irq_handler WWDG_IRQHandler
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def_irq_handler PVD_IRQHandler
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def_irq_handler TAMP_STAMP_IRQHandler
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def_irq_handler RTC_WKUP_IRQHandler
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def_irq_handler FLASH_IRQHandler
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def_irq_handler RCC_IRQHandler
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def_irq_handler EXTI0_IRQHandler
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def_irq_handler EXTI1_IRQHandler
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def_irq_handler EXTI2_IRQHandler
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def_irq_handler EXTI3_IRQHandler
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def_irq_handler EXTI4_IRQHandler
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def_irq_handler DMA1_Stream0_IRQHandler
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def_irq_handler DMA1_Stream1_IRQHandler
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def_irq_handler DMA1_Stream2_IRQHandler
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def_irq_handler DMA1_Stream3_IRQHandler
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def_irq_handler DMA1_Stream4_IRQHandler
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def_irq_handler DMA1_Stream5_IRQHandler
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def_irq_handler DMA1_Stream6_IRQHandler
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def_irq_handler ADC_IRQHandler
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def_irq_handler CAN1_TX_IRQHandler
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def_irq_handler CAN1_RX0_IRQHandler
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def_irq_handler CAN1_RX1_IRQHandler
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def_irq_handler CAN1_SCE_IRQHandler
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def_irq_handler EXTI9_5_IRQHandler
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def_irq_handler TIM1_BRK_TIM9_IRQHandler
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def_irq_handler TIM1_UP_TIM10_IRQHandler
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def_irq_handler TIM1_TRG_COM_TIM11_IRQHandler
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def_irq_handler TIM1_CC_IRQHandler
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def_irq_handler TIM2_IRQHandler
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def_irq_handler TIM3_IRQHandler
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def_irq_handler TIM4_IRQHandler
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def_irq_handler I2C1_EV_IRQHandler
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def_irq_handler I2C1_ER_IRQHandler
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def_irq_handler I2C2_EV_IRQHandler
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def_irq_handler I2C2_ER_IRQHandler
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def_irq_handler SPI1_IRQHandler
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def_irq_handler SPI2_IRQHandler
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def_irq_handler USART1_IRQHandler
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def_irq_handler USART2_IRQHandler
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def_irq_handler USART3_IRQHandler
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def_irq_handler EXTI15_10_IRQHandler
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def_irq_handler RTC_Alarm_IRQHandler
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def_irq_handler OTG_FS_WKUP_IRQHandler
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def_irq_handler TIM8_BRK_TIM12_IRQHandler
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def_irq_handler TIM8_UP_TIM13_IRQHandler
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def_irq_handler TIM8_TRG_COM_TIM14_IRQHandler
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def_irq_handler TIM8_CC_IRQHandler
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|
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def_irq_handler DMA1_Stream7_IRQHandler
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def_irq_handler FSMC_IRQHandler
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def_irq_handler SDIO_IRQHandler
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def_irq_handler TIM5_IRQHandler
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def_irq_handler SPI3_IRQHandler
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def_irq_handler UART4_IRQHandler
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def_irq_handler UART5_IRQHandler
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def_irq_handler TIM6_DAC_IRQHandler
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def_irq_handler TIM7_IRQHandler
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|
def_irq_handler DMA2_Stream0_IRQHandler
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def_irq_handler DMA2_Stream1_IRQHandler
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|
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def_irq_handler DMA2_Stream2_IRQHandler
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|
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def_irq_handler DMA2_Stream3_IRQHandler
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|
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def_irq_handler DMA2_Stream4_IRQHandler
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|
|
def_irq_handler ETH_IRQHandler
|
|
|
def_irq_handler ETH_WKUP_IRQHandler
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|
|
def_irq_handler CAN2_TX_IRQHandler
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|
|
def_irq_handler CAN2_RX0_IRQHandler
|
|
|
def_irq_handler CAN2_RX1_IRQHandler
|
|
|
def_irq_handler CAN2_SCE_IRQHandler
|
|
|
def_irq_handler OTG_FS_IRQHandler
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|
|
def_irq_handler DMA2_Stream5_IRQHandler
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|
|
def_irq_handler DMA2_Stream6_IRQHandler
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|
|
def_irq_handler DMA2_Stream7_IRQHandler
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|
|
def_irq_handler USART6_IRQHandler
|
|
|
def_irq_handler I2C3_EV_IRQHandler
|
|
|
def_irq_handler I2C3_ER_IRQHandler
|
|
|
def_irq_handler OTG_HS_EP1_OUT_IRQHandler
|
|
|
def_irq_handler OTG_HS_EP1_IN_IRQHandler
|
|
|
def_irq_handler OTG_HS_WKUP_IRQHandler
|
|
|
def_irq_handler OTG_HS_IRQHandler
|
|
|
def_irq_handler DCMI_IRQHandler
|
|
|
def_irq_handler CRYP_IRQHandler
|
|
|
def_irq_handler HASH_RNG_IRQHandler
|
|
|
def_irq_handler FPU_IRQHandler
|
|
|
|
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|
.end
|
|
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|
