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/**
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******************************************************************************
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* @file usb_conf.h
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* @author MCD Application Team
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* @version V2.1.0
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* @date 19-March-2012
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* @brief General low level driver configuration
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __USB_CONF__H__
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#define __USB_CONF__H__
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/* Includes ------------------------------------------------------------------*/
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#include "usb_conf.h"
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/** @addtogroup USB_OTG_DRIVER
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* @{
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*/
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/** @defgroup USB_CONF
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* @brief USB low level driver configuration file
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* @{
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*/
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/** @defgroup USB_CONF_Exported_Defines
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* @{
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*/
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/* USB Core and PHY interface configuration.
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Tip: To avoid modifying these defines each time you need to change the USB
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configuration, you can declare the needed define in your toolchain
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compiler preprocessor.
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*/
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/****************** USB OTG FS PHY CONFIGURATION *******************************
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* The USB OTG FS Core supports one on-chip Full Speed PHY.
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*
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* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor
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* when FS core is used.
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*******************************************************************************/
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#ifndef USE_USB_OTG_FS
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//#define USE_USB_OTG_FS
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#endif /* USE_USB_OTG_FS */
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#ifdef USE_USB_OTG_FS
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#define USB_OTG_FS_CORE
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#endif
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/****************** USB OTG HS PHY CONFIGURATION *******************************
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* The USB OTG HS Core supports two PHY interfaces:
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* (i) An ULPI interface for the external High Speed PHY: the USB HS Core will
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* operate in High speed mode
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* (ii) An on-chip Full Speed PHY: the USB HS Core will operate in Full speed mode
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*
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* You can select the PHY to be used using one of these two defines:
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* (i) USE_ULPI_PHY: if the USB OTG HS Core is to be used in High speed mode
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* (ii) USE_EMBEDDED_PHY: if the USB OTG HS Core is to be used in Full speed mode
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*
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* Notes:
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* - The USE_ULPI_PHY symbol is defined in the project compiler preprocessor as
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* default PHY when HS core is used.
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* - On STM322xG-EVAL and STM324xG-EVAL boards, only configuration(i) is available.
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* Configuration (ii) need a different hardware, for more details refer to your
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* STM32 device datasheet.
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*******************************************************************************/
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#ifndef USE_USB_OTG_HS
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//#define USE_USB_OTG_HS
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#endif /* USE_USB_OTG_HS */
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#ifndef USE_ULPI_PHY
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//#define USE_ULPI_PHY
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#endif /* USE_ULPI_PHY */
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#ifndef USE_EMBEDDED_PHY
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//#define USE_EMBEDDED_PHY
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#endif /* USE_EMBEDDED_PHY */
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#ifdef USE_USB_OTG_HS
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#define USB_OTG_HS_CORE
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#endif
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/*******************************************************************************
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* FIFO Size Configuration in Device mode
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*
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* (i) Receive data FIFO size = RAM for setup packets +
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* OUT endpoint control information +
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* data OUT packets + miscellaneous
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* Space = ONE 32-bits words
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* --> RAM for setup packets = 10 spaces
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* (n is the nbr of CTRL EPs the device core supports)
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* --> OUT EP CTRL info = 1 space
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* (one space for status information written to the FIFO along with each
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* received packet)
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* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces
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* (MINIMUM to receive packets)
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* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces
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* (if high-bandwidth EP is enabled or multiple isochronous EPs)
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* --> miscellaneous = 1 space per OUT EP
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* (one space for transfer complete status information also pushed to the
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* FIFO with each endpoint's last packet)
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*
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* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for
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* that particular IN EP. More space allocated in the IN EP Tx FIFO results
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* in a better performance on the USB and can hide latencies on the AHB.
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*
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* (iii) TXn min size = 16 words. (n : Transmit FIFO index)
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* (iv) When a TxFIFO is not used, the Configuration should be as follows:
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* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
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* --> Txm can use the space allocated for Txn.
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* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
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* --> Txn should be configured with the minimum space of 16 words
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* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top
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* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
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*******************************************************************************/
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/*******************************************************************************
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* FIFO Size Configuration in Host mode
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*
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* (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or
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* 2x (Largest Packet Size / 4) + 1, If a
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* high-bandwidth channel or multiple isochronous
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* channels are enabled
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*
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* (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size
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* for all supported nonperiodic OUT channels. Typically, a space
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* corresponding to two Largest Packet Size is recommended.
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*
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* (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is
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* the largest maximum packet size for all supported periodic OUT channels.
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* If there is at least one High Bandwidth Isochronous OUT endpoint,
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* then the space must be at least two times the maximum packet size for
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* that channel.
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*******************************************************************************/
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/****************** USB OTG HS CONFIGURATION **********************************/
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#ifdef USB_OTG_HS_CORE
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#define RX_FIFO_HS_SIZE 512
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#define TX0_FIFO_HS_SIZE 512
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#define TX1_FIFO_HS_SIZE 512
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#define TX2_FIFO_HS_SIZE 0
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#define TX3_FIFO_HS_SIZE 0
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#define TX4_FIFO_HS_SIZE 0
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#define TX5_FIFO_HS_SIZE 0
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#define TXH_NP_HS_FIFOSIZ 96
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#define TXH_P_HS_FIFOSIZ 96
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// #define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
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// #define USB_OTG_HS_SOF_OUTPUT_ENABLED
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// #define USB_OTG_INTERNAL_VBUS_ENABLED
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#define USB_OTG_EXTERNAL_VBUS_ENABLED
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#ifdef USE_ULPI_PHY
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#define USB_OTG_ULPI_PHY_ENABLED
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#endif
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#ifdef USE_EMBEDDED_PHY
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#define USB_OTG_EMBEDDED_PHY_ENABLED
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#endif
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#define USB_OTG_HS_INTERNAL_DMA_ENABLED
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#define USB_OTG_HS_DEDICATED_EP1_ENABLED
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#endif
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/****************** USB OTG FS CONFIGURATION **********************************/
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#ifdef USB_OTG_FS_CORE
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#define RX_FIFO_FS_SIZE 128
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#define TX0_FIFO_FS_SIZE 64
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#define TX1_FIFO_FS_SIZE 128
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#define TX2_FIFO_FS_SIZE 0
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#define TX3_FIFO_FS_SIZE 0
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#define TXH_NP_HS_FIFOSIZ 96
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#define TXH_P_HS_FIFOSIZ 96
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// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
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// #define USB_OTG_FS_SOF_OUTPUT_ENABLED
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#endif
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/****************** USB OTG MISC CONFIGURATION ********************************/
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//#define VBUS_SENSING_ENABLED
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/****************** USB OTG MODE CONFIGURATION ********************************/
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//#define USE_HOST_MODE
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#define USE_DEVICE_MODE
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//#define USE_OTG_MODE
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#ifndef USB_OTG_FS_CORE
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#ifndef USB_OTG_HS_CORE
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#error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined"
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#endif
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#endif
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#ifndef USE_DEVICE_MODE
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#ifndef USE_HOST_MODE
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#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
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#endif
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#endif
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#ifndef USE_USB_OTG_HS
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#ifndef USE_USB_OTG_FS
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#error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined"
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#endif
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#else //USE_USB_OTG_HS
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#ifndef USE_ULPI_PHY
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#ifndef USE_EMBEDDED_PHY
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#error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined"
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#endif
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#endif
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#endif
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/****************** C Compilers dependant keywords ****************************/
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/* In HS mode and when the DMA is used, all variables and data structures dealing
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with the DMA during the transaction process should be 4-bytes aligned */
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#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
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#if defined (__GNUC__) /* GNU Compiler */
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#define __ALIGN_END __attribute__ ((aligned (4)))
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#define __ALIGN_BEGIN
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#else
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#define __ALIGN_END
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#if defined (__CC_ARM) /* ARM Compiler */
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#define __ALIGN_BEGIN __align(4)
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#elif defined (__ICCARM__) /* IAR Compiler */
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#define __ALIGN_BEGIN
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#elif defined (__TASKING__) /* TASKING Compiler */
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#define __ALIGN_BEGIN __align(4)
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#endif /* __CC_ARM */
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#endif /* __GNUC__ */
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#else
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#define __ALIGN_BEGIN
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#define __ALIGN_END
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#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
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/* __packed keyword used to decrease the data type alignment to 1-byte */
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#if defined (__CC_ARM) /* ARM Compiler */
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#define __packed __packed
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#elif defined (__ICCARM__) /* IAR Compiler */
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#define __packed __packed
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#elif defined ( __GNUC__ ) /* GNU Compiler */
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#define __packed __attribute__ ((__packed__))
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#elif defined (__TASKING__) /* TASKING Compiler */
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#define __packed __unaligned
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#endif /* __CC_ARM */
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/**
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* @}
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*/
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/** @defgroup USB_CONF_Exported_Types
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup USB_CONF_Exported_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup USB_CONF_Exported_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup USB_CONF_Exported_FunctionsPrototype
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* @{
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*/
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/**
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* @}
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*/
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#endif //__USB_CONF__H__
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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