# HG changeset patch
# User Jeandet Alexis
# Date 2015-06-18 16:32:26
# Node ID 10ac2f44ce26fa88540967392c7f3f02c78e2448
# Parent  78cd1f963533dfdb1db18fd9812e33e1cc359d6d

Sync

diff --git a/qilib/qicadpcb.cpp b/qilib/qicadpcb.cpp
--- a/qilib/qicadpcb.cpp
+++ b/qilib/qicadpcb.cpp
@@ -241,7 +241,7 @@ void QIlib::QIcadPcbRoot::apendVia(QIlib
 {
     if(node->name==QIlib::Lexique::via_c)
     {
-        this->vias.append(new QIcadPcbVia(node));
+        this->vias.append(new QIcadPcbVia(node,this->setup.defaultViaDrillSize()));
     }
 }
 
@@ -749,7 +749,18 @@ QIlib::QIcadPcbSetup::QIcadPcbSetup(QIli
 
 void QIlib::QIcadPcbSetup::setNode(QIlib::AbstractNode *node)
 {
-    this->p_node = node;
+    if(node->name==QIlib::Lexique::setup_c)
+    {
+        this->p_node = node;
+        for(int i=0;i<node->nodes.count();i++)
+        {
+            if(node->nodes.at(i)->name==QIlib::Lexique::via_drill_c)
+            {
+                this->via_dril.setNode(node->nodes.at(i));
+                this->p_defaultViaDrillSize = nodeValueToDouble(node->nodes.at(i));
+            }
+        }
+    }
 }
 
 
@@ -807,8 +818,8 @@ void QIlib::QIcadPcbSegment::setNode(QIl
 }
 
 
-QIlib::QIcadPcbVia::QIcadPcbVia(QIlib::AbstractNode *node)
-    :QIcadAbstractNodeWrapper(node)
+QIlib::QIcadPcbVia::QIcadPcbVia(QIlib::AbstractNode *node, double defaultDrill)
+    :QIcadAbstractNodeWrapper(node),p_drill(defaultDrill)
 {
     this->setNode(node);
 }
@@ -828,7 +839,7 @@ void QIlib::QIcadPcbVia::setNode(QIlib::
             if(node->nodes.at(i)->name==QIlib::Lexique::size_c)
             {
                 this->sizeNode.setNode(node->nodes.at(i));
-                p_size = nodeTo2DSize(node->nodes.at(i));
+                p_size = QSizeF(nodeValueToDouble(node->nodes.at(i)),nodeValueToDouble(node->nodes.at(i)));
             }
             if(node->nodes.at(i)->name==QIlib::Lexique::drill_c)
             {
diff --git a/qilib/qicadpcb.h b/qilib/qicadpcb.h
--- a/qilib/qicadpcb.h
+++ b/qilib/qicadpcb.h
@@ -141,6 +141,9 @@ public:
     QIcadAbstractNodeWrapper visible_elements;
     QIcadPcbPlotParams plotParams;
     void setNode(QIlib::AbstractNode* node);
+    double defaultViaDrillSize(){return p_defaultViaDrillSize;}
+private:
+    double p_defaultViaDrillSize;
 };
 
 class QIcadPcbNetClass : public QIcadAbstractNodeWrapper
@@ -319,7 +322,7 @@ public:
 class QIcadPcbVia : public QIcadAbstractNodeWrapper
 {
 public:
-    QIcadPcbVia(QIlib::AbstractNode* node);
+    QIcadPcbVia(QIlib::AbstractNode* node, double defaultDrill=0);
     QIcadPcbVia(){}
     QIcadAbstractNodeWrapper at;
     QIcadAbstractNodeWrapper sizeNode;
diff --git a/test/PCBView/pcbvia.cpp b/test/PCBView/pcbvia.cpp
--- a/test/PCBView/pcbvia.cpp
+++ b/test/PCBView/pcbvia.cpp
@@ -45,13 +45,15 @@ void PCBVia::init(QPointF offset)
     {
         QGraphicsEllipseItem* ellipse = new QGraphicsEllipseItem();
         QPen pen = ellipse->pen();
-        pen.setWidthF(0.01);
+        double thickness = (this->viaNode->size().width()-this->viaNode->drill())/2;
+        pen.setWidthF(thickness);
+
         ellipse->setPen(pen);
-        QBrush brush = ellipse->brush();
-        brush.setStyle(Qt::SolidPattern);
-        brush.setColor(context->layerColor(this->viaNode->layers().at(i)));
-        ellipse->setBrush(brush);
-        QRectF rec(this->viaNode->pos()+offset,this->viaNode->size());
+//        QBrush brush = ellipse->brush();
+//        brush.setStyle(Qt::SolidPattern);
+//        brush.setColor(context->layerColor(this->viaNode->layers().at(i)));
+//        ellipse->setBrush(brush);
+        QRectF rec(this->viaNode->pos()+offset,QSizeF(this->viaNode->size().width()-thickness,this->viaNode->size().width()-thickness));
         ellipse->setRect(rec);
         ellipse->setZValue(-context->layer(viaNode->layers().at(i)));
         this->addToGroup(ellipse);