register the data outputed by ADC_driver

temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

temp

temp

ADD SDC constraint

merge simu_with_leon3 (add lpp_dma_SEND16B_FIFO2DMA)

update ok ??

force ADC output to constant or ramp.

global reset delayed in function of ram_nbusy signal (waiting 16 falling edge).

temp JC