KEY LIBERO "9.0"
KEY CAPTURE "9.0.0.15"
KEY DEFAULT_IMPORT_LOC "D:\GRLIB_BusAMBA\VHD_Lib\lib\lpp\lpp_matrix"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "9436de63-fded-4f73-8745-68ca6f0f141d"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "ProASIC3"
KEY VendorTechnology_Die "M7IS8X8M2"
KEY VendorTechnology_Package "fg484"
KEY ProjectLocation "C:\opt\GRLIB\grlib-ft-fpga-1.0.21-b4003\designs\TEST-LEON-M7-LPP"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
CURREV=2
ENDLIST
LIST LIBRARIES
grlib
proasic3
synplify
techmap
spw
eth
opencores
gaisler
esa
fmf
spansion
gsi
lpp
cypress
ENDLIST
LIST LIBRARY_grlib
ALIAS=grlib
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_proasic3
ALIAS=proasic3
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_synplify
ALIAS=synplify
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_techmap
ALIAS=techmap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spw
ALIAS=spw
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_eth
ALIAS=eth
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_opencores
ALIAS=opencores
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gaisler
ALIAS=gaisler
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_esa
ALIAS=esa
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_fmf
ALIAS=fmf
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spansion
ALIAS=spansion
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gsi
ALIAS=gsi
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_lpp
ALIAS=lpp
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_cypress
ALIAS=cypress
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
VALUE "<project>\..\..\\boards\TEST-LEON-M7-LPP\TEST-LEON-M7-LPP.pdc,pdc"
STATE="utd"
TIME="1314194811"
SIZE="5135"
ENDFILE
VALUE "<project>\..\..\\lib\cypress\ssram\components.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6172"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="16395"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="26462"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\\lib\cypress\ssram\package_utility.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2040"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\\lib\esa\memoryctrl\mctrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="35904"
LIBRARY="esa"
ENDFILE
VALUE "<project>\..\..\\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2150"
LIBRARY="esa"
ENDFILE
VALUE "<project>\..\..\\lib\eth\comp\ethcomp.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="15187"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\eth_ahb_mst.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5880"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\eth_rstgen.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="1891"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\grethc.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="66506"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\greth_pkg.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="19491"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\greth_rx.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="10381"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\greth_tx.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="16396"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="10160"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\wrapper\greth_gen.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="10341"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\fmf\utilities\conversions.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="39795"
LIBRARY="fmf"
ENDFILE
VALUE "<project>\..\..\\lib\fmf\utilities\gen_utils.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5981"
LIBRARY="fmf"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbmst_em.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="8910"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbslv_em.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6496"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6721"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="20524"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\arith\arith.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3806"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\arith\div32.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5817"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\arith\mul32.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="14212"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\can\can.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5489"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\can\canmux.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="895"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\can\can_mc.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6104"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\can\can_mod.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5455"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\can\can_oc.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5485"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\can\can_rd.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6590"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\greth\ethernet_mac.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6371"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\greth\greth.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="11006"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\greth\grethm.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3723"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\greth\greth_gbit.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="9924"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\jtag\ahbjtag.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3933"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2973"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\jtag\jtag.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3199"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\jtag\jtagcom.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5510"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="13849"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\jtag\libjtagcom.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2190"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\acache.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="10085"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\cache.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4459"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\cachemem.vhd,hdl"
STATE="utd"
TIME="1211121356"
SIZE="18464"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\cpu_disasx.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2381"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\dcache.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="44265"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\dsu3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2374"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\dsu3x.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="24511"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\grfpushwx.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="10068"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\grfpwx.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="9264"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\grfpwxsh.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="9517"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\grlfpwx.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="9049"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\icache.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="22124"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\irqmp.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="7707"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\iu3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="110342"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\leon3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="26866"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\leon3cg.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="7600"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\leon3s.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="7651"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\leon3sh.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="7105"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\libcache.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="23375"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\libiu.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="8934"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\libmmu.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="7944"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\libproc3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5988"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mfpwx.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="7228"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmu.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="18536"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmuconfig.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="16283"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmuiface.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="7583"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmulru.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5263"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmulrue.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3049"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmutlb.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="20680"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmutlbcam.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6912"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmutw.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="8278"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmu_acache.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="12676"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmu_cache.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4966"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmu_dcache.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="60138"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\mmu_icache.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="23798"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\proc3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="7022"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\leon3\tbufmem.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2091"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\memctrl\memctrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="29070"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\memctrl\sdctrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="20662"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="18379"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\memctrl\srctrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="13959"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\ahbdma.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5521"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\ahbmst.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5350"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\ahbram.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4241"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\ahbstat.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4260"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\ahbtrace.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="11104"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\apbps2.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="13132"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\apbvga.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="11816"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\charrom.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="119168"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\charrom_package.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="1644"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\gptimer.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="9659"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\grgpio.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="8231"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\i2cslv.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="19789"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\logan.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="16852"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\misc.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="25471"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\rstgen.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2509"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\spictrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="24377"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\svgactrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="21077"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\wild.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5863"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\misc\wild2ahb.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="22613"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\net\net.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6963"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\sim\ahbrep.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5088"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\sim\ata_device.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="15636"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\sim\i2c_slave_model.v,hdl"
STATE="utd"
TIME="1208957498"
SIZE="11656"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\sim\phy.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="23511"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\sim\sim.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="15670"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\sim\sram.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5140"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\sim\sram16.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2251"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\spacewire\grspw.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="14998"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\spacewire\grspw2.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="11651"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\spacewire\grspwm.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3863"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\spacewire\spacewire.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6484"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\uart\ahbuart.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2599"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\uart\apbuart.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="16821"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\uart\dcom.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4871"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\uart\dcom_uart.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="9652"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\uart\libdcom.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5259"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\gaisler\uart\uart.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2578"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\amba\ahbctrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="26677"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\amba\amba.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="21797"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\amba\apbctrl.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="9001"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\amba\defmst.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="1865"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\amba\devices.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="28860"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\amba\dma2ahb.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="25098"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6002"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="63758"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\modgen\leaves.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="682913"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\modgen\multlib.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="1614"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\sparc\cpu_disas.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4248"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\sparc\sparc.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="9956"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\sparc\sparc_disas.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="27297"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\stdlib\stdio.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="8483"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\stdlib\stdlib.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="13002"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\stdlib\version.vhd,hdl"
STATE="utd"
TIME="1211121312"
SIZE="270"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\grlib\util\util.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="1711"
LIBRARY="grlib"
ENDFILE
VALUE "<project>\..\..\\lib\gsi\ssram\core_burst.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="18591"
LIBRARY="gsi"
ENDFILE
VALUE "<project>\..\..\\lib\gsi\ssram\functions.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="97832"
LIBRARY="gsi"
ENDFILE
VALUE "<project>\..\..\\lib\gsi\ssram\g880e18bt.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6801"
LIBRARY="gsi"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\amba_lcd_16x2_ctrlr\amba_lcd_16x2_ctrlr.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4857"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\amba_lcd_16x2_ctrlr\apb_lcd_ctrlr.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4684"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\amba_lcd_16x2_ctrlr\FRAME_CLK.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2063"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_CFG.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2262"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_DRVR.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4068"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_ENGINE.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="5400"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_2x16_DRIVER.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4608"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_CLK_GENERATOR.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2035"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\amba_lcd_16x2_ctrlr\Top_LCD.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3093"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="141869"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4032"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\APB_FFT.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4086"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="12457"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="25871"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="32249"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="5049"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\Flag_Extremum.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2586"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="5180"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3997"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="12080"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\Adder.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2272"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1930"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\ALU.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2278"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1958"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="5897"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\MAC.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="7280"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1961"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1985"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1710"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1775"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2230"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1692"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\REG.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1812"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2198"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3844"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_ad_Conv\AD7688_spi_if.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2498"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2995"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3758"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_ad_Conv\lpp_apb_ad_conv.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4391"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1280"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_amba\APB_MULTI_DIODE.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3238"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_amba\APB_SIMPLE_DIODE.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3455"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2548"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_AMR\APB_AMR.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3577"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_AMR\bclk_reg.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="685"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_AMR\Clock_multi.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1218"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_AMR\Dephaseur.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1492"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_AMR\Gene_Rz.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1011"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_AMR\lpp_AMR.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2523"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_balise\APB_Balise.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4392"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_balise\lpp_balise.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1887"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_cna\APB_CNA.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4480"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_cna\CNA_TabloC.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3111"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_cna\Convertisseur_config.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="1626"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_cna\Gene_SYNC.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2613"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2946"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_cna\Serialize.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3956"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_cna\Systeme_Clock.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2338"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="8207"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\ALU_v2.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2878"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\APB_Matrix.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="5130"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4310"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3184"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="7820"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\MAC_v2.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="9200"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3047"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\SelectInputs.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="5834"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3837"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\Starter.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3160"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_matrix\TwoComplementer.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="2848"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_memory\ApbDriver.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="6880"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_memory\APB_FIFO.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3314"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_memory\APB_FifoRead.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3733"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_memory\APB_FifoWrite.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3758"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_memory\Fifo_Read.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3600"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_memory\Fifo_Write.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3277"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_memory\Link_Reg.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3623"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="8299"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_memory\Top_FIFO.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="5025"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_uart\APB_UART.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="5120"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_uart\BaudGen.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3871"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_uart\lpp_uart.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3792"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_uart\Shift_REG.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4387"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_uart\UART.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4233"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_usb\APB_USB.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="4054"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_usb\lpp_usb.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="3039"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\lpp\.\lpp_usb\RWbuf.vhd,hdl"
STATE="utd"
TIME="1316008876"
SIZE="5486"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\\lib\opencores\can\cancomp.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3227"
LIBRARY="opencores"
ENDFILE
VALUE "<project>\..\..\\lib\opencores\can\can_top.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="356774"
LIBRARY="opencores"
ENDFILE
VALUE "<project>\..\..\\lib\opencores\can\can_top_core_sync.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="157516"
LIBRARY="opencores"
ENDFILE
VALUE "<project>\..\..\\lib\opencores\occomp\occomp.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="8547"
LIBRARY="opencores"
ENDFILE
VALUE "<project>\..\..\\lib\spw\comp\spwcomp.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="15964"
LIBRARY="spw"
ENDFILE
VALUE "<project>\..\..\\lib\synplify\sim\synattr.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="22767"
LIBRARY="synplify"
ENDFILE
VALUE "<project>\..\..\\lib\synplify\sim\synplify.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="9340"
LIBRARY="synplify"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\gencomp\gencomp.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="30989"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\gencomp\netcomp.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="31710"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\inferred\ddr_inferred.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2249"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\inferred\memory_inferred.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5207"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\inferred\mul_inferred.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2183"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\allclkgen.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="10347"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\allddr.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="14594"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\allmem.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="22973"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\allpads.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="15060"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\alltap.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5468"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\clkand.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2181"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\clkgen.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5982"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\clkmux.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2612"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\clkpad.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3185"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\clkpad_ds.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2248"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\cpu_disas_net.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4450"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\ddrphy.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="10089"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\ddr_ireg.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2043"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\ddr_oreg.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2142"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\grfpw_net.vhd,hdl"
STATE="utd"
TIME="1313657978"
SIZE="32598"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\grlfpw_net.vhd,hdl"
STATE="utd"
TIME="1309254878"
SIZE="36805"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\grspwc_net.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="17903"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\inpad.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3800"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\inpad_ds.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2820"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\iodpad.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4267"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\iopad.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5277"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\iopad_ds.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3749"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\lvds_combo.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3315"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\mul_61x61.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2354"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\odpad.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4334"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\outpad.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4148"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\outpad_ds.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3001"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\regfile_3p.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3072"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\ringosc.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="1934"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\skew_outpad.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2076"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\ssrctrl_net.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="12187"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\syncfifo.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2931"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\syncram.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6173"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\syncram64.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4010"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\syncram_2p.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6732"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\syncram_dp.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5126"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\tap.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4941"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\techbuf.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2814"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\toutpad.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="5195"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\maps\usbhc_net.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="49497"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\proasic3\buffer_apa3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2154"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\proasic3\clkgen_proasic3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="6738"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\proasic3\memory_apa3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="17067"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\techmap\proasic3\tap_proasic3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="3674"
LIBRARY="techmap"
ENDFILE
VALUE "<project>\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="115108"
LIBRARY="proasic3"
ENDFILE
VALUE "<project>\..\..\\lib\work\debug\cpu_disas.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4162"
ENDFILE
VALUE "<project>\..\..\\lib\work\debug\debug.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="1675"
ENDFILE
VALUE "<project>\..\..\\lib\work\debug\grtestmod.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="4683"
ENDFILE
VALUE "<project>\ahbrom.vhd,hdl"
STATE="utd"
TIME="1314194813"
SIZE="9014"
ENDFILE
VALUE "<project>\config.vhd,hdl"
STATE="utd"
TIME="1316609032"
SIZE="6145"
ENDFILE
VALUE "<project>\designer\impl2\top.adb,adb"
STATE="ood"
TIME="1316518304"
SIZE="3168256"
ENDFILE
VALUE "<project>\designer\impl2\top.pdb,pdb"
STATE="ood"
TIME="1316518292"
SIZE="1591296"
ENDFILE
VALUE "<project>\designer\impl2\top_fp\top.pro,pro"
STATE="utd"
TIME="1316092826"
SIZE="2023"
ENDFILE
VALUE "<project>\leon3mp.vhd,hdl"
STATE="utd"
TIME="1316444842"
SIZE="13491"
ENDFILE
VALUE "<project>\synthesis\top.edn,syn_edn"
STATE="ood"
TIME="1316518141"
SIZE="1633458"
ENDFILE
VALUE "<project>\synthesis\top_sdc.sdc,syn_sdc"
STATE="ood"
TIME="1316518141"
SIZE="381"
ENDFILE
VALUE "C:\opt\GRLIB\grlib-ft-fpga-1.0.21-b4003\boards\TEST-LEON-M7-LPP\TEST-LEON-M7-LPP.pdc,pdc"
STATE="utd"
TIME="1314194811"
SIZE="5135"
IS_READONLY="TRUE"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "top::work"
FILE "<project>\leon3mp.vhd,hdl"
LIST ExcludePackageForSynthesis
VALUE "<project>\..\..\\lib\grlib\stdlib\stdio.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\util\util.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\sparc\sparc_disas.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\sparc\cpu_disas.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
VALUE "<project>\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl"
VALUE "<project>\..\..\\lib\synplify\sim\synplify.vhd,hdl"
VALUE "<project>\..\..\\lib\synplify\sim\synattr.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbslv_em.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbmst_em.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\i2c_slave_model.v,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sim.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sram.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\ata_device.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sram16.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\phy.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\ahbrep.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl"
VALUE "<project>\..\..\\lib\fmf\utilities\conversions.vhd,hdl"
VALUE "<project>\..\..\\lib\fmf\utilities\gen_utils.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\functions.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\core_burst.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\g880e18bt.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\components.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\package_utility.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\debug.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\grtestmod.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\cpu_disas.vhd,hdl"
VALUE "<project>\config.vhd,hdl"
VALUE "<project>\ahbrom.vhd,hdl"
VALUE "<project>\leon3mp.vhd,hdl"
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="Synplify AE"
FUNCTION="Synthesis"
TOOL="Synplify"
LOCATION="C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\bin\synplify_pro.exe"
PARAM=""
BATCH=0
EndProfile
NAME="ModelSim AE"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Actel\Libero_v9.0\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
EndProfile
NAME="WFL"
FUNCTION="Stimulus"
TOOL="WFL"
LOCATION="syncad.exe"
PARAM="-pwflite"
BATCH=0
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Actel\Libero_v9.0\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
EndProfile
ENDLIST
LIST ProjectState5.1
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
LIST top
VALUE "<project>\..\..\\lib\grlib\stdlib\stdio.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\util\util.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\sparc\sparc_disas.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\sparc\cpu_disas.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
VALUE "<project>\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl"
VALUE "<project>\..\..\\lib\synplify\sim\synplify.vhd,hdl"
VALUE "<project>\..\..\\lib\synplify\sim\synattr.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbslv_em.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbmst_em.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\i2c_slave_model.v,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sim.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sram.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\ata_device.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sram16.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\phy.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\ahbrep.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl"
VALUE "<project>\..\..\\lib\fmf\utilities\conversions.vhd,hdl"
VALUE "<project>\..\..\\lib\fmf\utilities\gen_utils.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\functions.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\core_burst.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\g880e18bt.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\components.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\package_utility.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\debug.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\grtestmod.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\cpu_disas.vhd,hdl"
VALUE "<project>\config.vhd,hdl"
VALUE "<project>\ahbrom.vhd,hdl"
VALUE "<project>\leon3mp.vhd,hdl"
ENDLIST
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
FILE:<project>\leon3mp.vhd,hdl
FILE:<project>\config.vhd,hdl
FILE:<project>\..\..\\lib\techmap\proasic3\clkgen_proasic3.vhd,hdl
ACTIVE_VIEW:1
ENDLIST