KEY LIBERO "9.0"
KEY CAPTURE "9.0.0.15"
KEY DEFAULT_IMPORT_LOC "D:\GRLIB_BusAMBA\VHD_Lib\lib\lpp\lpp_matrix"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "61b9fca3-f638-4c85-ae3c-7f116ad7dbed"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "ProASIC3"
KEY VendorTechnology_Die "M7IS8X8M2"
KEY VendorTechnology_Package "fg484"
KEY ProjectLocation "C:\opt\GRLIB\grlib-ft-fpga-1.0.21-b4003\designs\leon3-actel-coremp7"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "leon3mp::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
CURREV=2
ENDLIST
LIST LIBRARIES
grlib
proasic3
synplify
techmap
spw
eth
opencores
gaisler
esa
fmf
spansion
gsi
lpp
cypress
ENDLIST
LIST LIBRARY_grlib
ALIAS=grlib
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_proasic3
ALIAS=proasic3
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_synplify
ALIAS=synplify
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_techmap
ALIAS=techmap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spw
ALIAS=spw
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_eth
ALIAS=eth
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_opencores
ALIAS=opencores
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gaisler
ALIAS=gaisler
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_esa
ALIAS=esa
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_fmf
ALIAS=fmf
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spansion
ALIAS=spansion
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gsi
ALIAS=gsi
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_lpp
ALIAS=lpp
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_cypress
ALIAS=cypress
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
VALUE "<project>\..\..\\lib\cypress\ssram\components.vhd,hdl"
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TIME="1210769968"
SIZE="6172"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="16395"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="26462"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\\lib\cypress\ssram\package_utility.vhd,hdl"
STATE="utd"
TIME="1210769968"
SIZE="2040"
LIBRARY="cypress"
ENDFILE
VALUE "<project>\..\..\\lib\esa\memoryctrl\mctrl.vhd,hdl"
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SIZE="35904"
LIBRARY="esa"
ENDFILE
VALUE "<project>\..\..\\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
STATE="utd"
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SIZE="2150"
LIBRARY="esa"
ENDFILE
VALUE "<project>\..\..\\lib\eth\comp\ethcomp.vhd,hdl"
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LIBRARY="eth"
ENDFILE
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LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\eth_rstgen.vhd,hdl"
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LIBRARY="eth"
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VALUE "<project>\..\..\\lib\eth\core\grethc.vhd,hdl"
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LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\greth_pkg.vhd,hdl"
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LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\greth_rx.vhd,hdl"
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LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\core\greth_tx.vhd,hdl"
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LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
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SIZE="10160"
LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\eth\wrapper\greth_gen.vhd,hdl"
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LIBRARY="eth"
ENDFILE
VALUE "<project>\..\..\\lib\fmf\utilities\conversions.vhd,hdl"
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LIBRARY="fmf"
ENDFILE
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ENDFILE
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ENDFILE
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ENDFILE
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\\lib\gaisler\jtag\jtag.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\\lib\gaisler\jtag\jtagcom.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\\lib\gaisler\jtag\libjtagcom.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\\lib\gaisler\leon3\grfpushwx.vhd,hdl"
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ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "leon3mp::work"
FILE "<project>\leon3mp.vhd,hdl"
LIST ExcludePackageForSynthesis
VALUE "<project>\..\..\\lib\grlib\stdlib\stdio.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\util\util.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\sparc\sparc_disas.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\sparc\cpu_disas.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
VALUE "<project>\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl"
VALUE "<project>\..\..\\lib\synplify\sim\synplify.vhd,hdl"
VALUE "<project>\..\..\\lib\synplify\sim\synattr.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbslv_em.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbmst_em.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\i2c_slave_model.v,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sim.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sram.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\ata_device.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sram16.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\phy.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\ahbrep.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl"
VALUE "<project>\..\..\\lib\fmf\utilities\conversions.vhd,hdl"
VALUE "<project>\..\..\\lib\fmf\utilities\gen_utils.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\functions.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\core_burst.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\g880e18bt.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\components.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\package_utility.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\debug.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\grtestmod.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\cpu_disas.vhd,hdl"
VALUE "<project>\config.vhd,hdl"
VALUE "<project>\ahbrom.vhd,hdl"
VALUE "<project>\leon3mp.vhd,hdl"
VALUE "<project>\testbench.vhd,hdl"
ENDLIST
LIST SynthesisConstraints
VALUE "<project>\leon3mp.sdc,sdc"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateFailure
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateFailure
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="Synplify AE"
FUNCTION="Synthesis"
TOOL="Synplify"
LOCATION="C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\bin\synplify_pro.exe"
PARAM=""
BATCH=0
EndProfile
NAME="ModelSim AE"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Actel\Libero_v9.0\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
EndProfile
NAME="WFL"
FUNCTION="Stimulus"
TOOL="WFL"
LOCATION="syncad.exe"
PARAM="-pwflite"
BATCH=0
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Actel\Libero_v9.0\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "leon3mp::work"
LIST Impl1
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateFailure
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateFailure
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
LIST leon3mp
VALUE "<project>\..\..\\lib\grlib\stdlib\stdio.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\util\util.vhd,hdl"
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VALUE "<project>\..\..\\lib\grlib\sparc\cpu_disas.vhd,hdl"
VALUE "<project>\..\..\\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
VALUE "<project>\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl"
VALUE "<project>\..\..\\lib\synplify\sim\synplify.vhd,hdl"
VALUE "<project>\..\..\\lib\synplify\sim\synattr.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbslv_em.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\ambatest\ahbmst_em.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\i2c_slave_model.v,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sim.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sram.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\ata_device.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\sram16.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\phy.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\sim\ahbrep.vhd,hdl"
VALUE "<project>\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl"
VALUE "<project>\..\..\\lib\fmf\utilities\conversions.vhd,hdl"
VALUE "<project>\..\..\\lib\fmf\utilities\gen_utils.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\functions.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\core_burst.vhd,hdl"
VALUE "<project>\..\..\\lib\gsi\ssram\g880e18bt.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\components.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\package_utility.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl"
VALUE "<project>\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\debug.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\grtestmod.vhd,hdl"
VALUE "<project>\..\..\\lib\work\debug\cpu_disas.vhd,hdl"
VALUE "<project>\config.vhd,hdl"
VALUE "<project>\ahbrom.vhd,hdl"
VALUE "<project>\leon3mp.vhd,hdl"
VALUE "<project>\testbench.vhd,hdl"
ENDLIST
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
FILE:<project>\leon3mp.vhd,hdl
FILE:<project>\ahbrom.vhd,hdl
FILE:<project>\config.vhd,hdl
FILE:<project>\..\..\\lib\lpp\.\lpp_usb\RWbuf.vhd,hdl
FILE:<project>\..\..\\lib\techmap\maps\techbuf.vhd,hdl
FILE:<project>\..\..\\lib\gaisler\greth\greth.vhd,hdl
FILE:<project>\..\..\\lib\grlib\amba\apbctrl.vhd,hdl
FILE:<project>\..\..\\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl
FILE:<project>\..\..\\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl
FILE:<project>\..\..\\lib\techmap\proasic3\clkgen_proasic3.vhd,hdl
ACTIVE_VIEW:10
ENDLIST