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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: gencomp
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-- File: gencomp.vhd
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-- Author: Jiri Gaisler et al. - Aeroflex Gaisler
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-- Description: Declaration of portable memory modules, pads, e.t.c.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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package gencomp is
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---------------------------------------------------------------------------
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-- BASIC DECLARATIONS
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---------------------------------------------------------------------------
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-- technologies and libraries
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constant NTECH : integer := 46;
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type tech_ability_type is array (0 to NTECH) of integer;
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constant inferred : integer := 0;
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constant virtex : integer := 1;
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constant virtex2 : integer := 2;
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constant memvirage : integer := 3;
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constant axcel : integer := 4;
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constant proasic : integer := 5;
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constant atc18s : integer := 6;
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constant altera : integer := 7;
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constant umc : integer := 8;
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constant rhumc : integer := 9;
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constant apa3 : integer := 10;
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constant spartan3 : integer := 11;
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constant ihp25 : integer := 12;
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constant rhlib18t : integer := 13;
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constant virtex4 : integer := 14;
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constant lattice : integer := 15;
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constant ut25 : integer := 16;
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constant spartan3e : integer := 17;
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constant peregrine : integer := 18;
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constant memartisan : integer := 19;
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constant virtex5 : integer := 20;
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constant custom1 : integer := 21;
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constant ihp25rh : integer := 22;
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constant stratix1 : integer := 23;
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constant stratix2 : integer := 24;
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constant eclipse : integer := 25;
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constant stratix3 : integer := 26;
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constant cyclone3 : integer := 27;
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constant memvirage90 : integer := 28;
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constant tsmc90 : integer := 29;
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constant easic90 : integer := 30;
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constant atc18rha : integer := 31;
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constant smic013 : integer := 32;
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constant tm65gpl : integer := 33;
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constant axdsp : integer := 34;
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constant spartan6 : integer := 35;
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constant virtex6 : integer := 36;
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constant actfus : integer := 37;
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constant stratix4 : integer := 38;
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constant st65lp : integer := 39;
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constant st65gp : integer := 40;
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constant easic45 : integer := 41;
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constant cmos9sf : integer := 42;
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constant apa3e : integer := 43;
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constant apa3l : integer := 44;
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constant ut130 : integer := 45;
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constant ut90 : integer := 46;
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constant DEFMEMTECH : integer := inferred;
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constant DEFPADTECH : integer := inferred;
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constant DEFFABTECH : integer := inferred;
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constant is_fpga : tech_ability_type :=
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(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
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proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
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virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
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stratix1 => 1, stratix2 => 1, eclipse => 1,
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stratix3 => 1, cyclone3 => 1, axdsp => 1,
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spartan6 => 1, virtex6 => 1, actfus => 1,
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stratix4 => 1, apa3e => 1, apa3l => 1,
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others => 0);
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constant infer_mul : tech_ability_type := is_fpga;
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constant syncram_2p_write_through : tech_ability_type :=
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(rhumc => 1, eclipse => 1, others => 0);
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constant regfile_3p_write_through : tech_ability_type :=
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(rhumc => 1, ihp25 => 1, ihp25rh => 1, eclipse => 1, others => 0);
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constant regfile_3p_infer : tech_ability_type :=
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(inferred => 1, rhumc => 1, ihp25 => 1, rhlib18t => 0,
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peregrine => 1, ihp25rh => 1, umc => 1, custom1 => 0, others => 0);
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constant syncram_2p_dest_rw_collision : tech_ability_type :=
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(memartisan => 1, smic013 => 1, easic45 => 1, others => 0);
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constant syncram_dp_dest_rw_collision : tech_ability_type :=
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(memartisan => 1, smic013 => 1, others => 0);
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constant has_sram : tech_ability_type :=
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(atc18s => 0, others => 1);
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constant has_2pram : tech_ability_type :=
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( atc18s => 0, umc => 0, rhumc => 0, ihp25 => 0, others => 1);
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constant has_dpram : tech_ability_type :=
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(virtex => 1, virtex2 => 1, memvirage => 1, axcel => 1,
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altera => 1, apa3 => 1, spartan3 => 1, virtex4 => 1,
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lattice => 1, spartan3e => 1, memartisan => 1, virtex5 => 1,
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custom1 => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
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cyclone3 => 1, memvirage90 => 1, atc18rha => 1, smic013 => 1,
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tm65gpl => 1, axdsp => 1, spartan6 => 1, virtex6 => 1,
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actfus => 1, stratix4 => 1, easic45 => 1, apa3e => 1,
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apa3l => 1, ut90 => 1, others => 0);
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constant has_sram64 : tech_ability_type :=
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(inferred => 0, virtex2 => 1, spartan3 => 1, virtex4 => 1,
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spartan3e => 1, memartisan => 1, virtex5 => 1, smic013 => 1,
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spartan6 => 1, virtex6 => 1, others => 0);
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constant padoen_polarity : tech_ability_type :=
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(axcel => 1, proasic => 1, umc => 1, rhumc => 1, apa3 => 1,
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ihp25 => 1, ut25 => 1, peregrine => 1, easic90 => 1, axdsp => 1,
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actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
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ut90 => 1, others => 0);
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constant has_pads : tech_ability_type :=
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(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
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axcel => 1, proasic => 1, atc18s => 1, altera => 0,
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umc => 1, rhumc => 1, apa3 => 1, spartan3 => 1,
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ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 0,
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ut25 => 1, spartan3e => 1, peregrine => 1, virtex5 => 1, axdsp => 1,
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easic90 => 1, atc18rha => 1, spartan6 => 1, virtex6 => 1,
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actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
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ut90 => 1, others => 0);
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constant has_ds_pads : tech_ability_type :=
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(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
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axcel => 1, proasic => 0, atc18s => 0, altera => 0,
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umc => 0, rhumc => 0, apa3 => 1, spartan3 => 1,
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ihp25 => 0, rhlib18t => 1, virtex4 => 1, lattice => 0,
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ut25 => 1, spartan3e => 1, virtex5 => 1, axdsp => 1,
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spartan6 => 1, virtex6 => 1, actfus => 1,
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apa3e => 1, apa3l => 1, ut130 => 0, easic45 => 1,
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others => 0);
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constant has_ds_combo : tech_ability_type :=
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( rhumc => 1, ut25 => 1, ut130 => 1, others => 0);
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constant has_clkand : tech_ability_type :=
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( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
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virtex5 => 1, ut25 => 1, rhlib18t => 1,
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spartan6 => 1, virtex6 => 1, ut130 => 1, easic45 => 1,
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others => 0);
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constant has_clkmux : tech_ability_type :=
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( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1,
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virtex4 => 1, virtex5 => 1, rhlib18t => 1,
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spartan6 => 1, virtex6 => 1, ut130 => 1, others => 0);
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constant has_techbuf : tech_ability_type :=
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( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
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spartan3 => 1, spartan3e => 1, axcel => 1, ut25 => 1,
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apa3 => 1, easic90 => 1, axdsp => 1, actfus => 1,
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apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
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spartan6 => 1, others => 0);
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constant has_tapsel : tech_ability_type :=
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( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
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spartan3 => 1, spartan3e => 1,
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spartan6 => 1, virtex6 => 1, others => 0);
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constant need_extra_sync_reset : tech_ability_type :=
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(axcel => 1, atc18s => 1, ut25 => 1, rhumc => 1, tsmc90 => 1,
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rhlib18t => 1, atc18rha => 1, easic90 => 1, tm65gpl => 1,
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axdsp => 1, cmos9sf => 1, apa3 => 1, apa3e => 1, apa3l => 1,
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ut130 => 1, others => 0);
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constant is_unisim : tech_ability_type :=
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( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
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spartan3 => 1, spartan3e => 1,
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spartan6 => 1, virtex6 => 1, others => 0);
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constant has_tap : tech_ability_type :=
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(inferred => 0, virtex => 1, virtex2 => 1, axcel => 0,
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proasic => 0, altera => 1, apa3 => 1, spartan3 => 1,
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virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
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stratix1 => 1, stratix2 => 1, eclipse => 0,
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stratix3 => 1, cyclone3 => 1, axdsp => 0,
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spartan6 => 1, virtex6 => 1, actfus => 1,
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stratix4 => 1, easic45 => 0, apa3e => 1, apa3l => 1,
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others => 0);
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constant has_clkgen : tech_ability_type :=
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(inferred => 0, virtex => 1, virtex2 => 1, axcel => 1,
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proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
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virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
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stratix1 => 1, stratix2 => 1, eclipse => 0, rhumc => 1,
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stratix3 => 1, cyclone3 => 1, axdsp => 1,
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spartan6 => 1, virtex6 => 1, actfus => 1, easic90 => 1,
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stratix4 => 1, easic45 => 1, apa3e => 1, apa3l => 1,
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rhlib18t => 1, ut130 => 1, others => 0);
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constant has_ddr2phy: tech_ability_type :=
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(inferred => 0, stratix2 => 1, stratix3 => 1, spartan3 => 1,
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easic90 => 1, spartan6 => 1, easic45 => 1,
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virtex4 => 1, virtex5 => 1, virtex6 => 1, others => 0);
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constant ddr2phy_has_cb: tech_ability_type :=
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(inferred => 1, virtex4 => 1, virtex5 => 1, virtex6 => 1, others => 0);
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constant ddr2phy_has_reg: tech_ability_type :=
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(easic45 => 1, others => 0);
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constant ddr2phy_refclk_type: tech_ability_type :=
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(virtex4 => 1, virtex5 => 1, virtex6 => 1, -- 1: 200 MHz reference
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easic45 => 2, -- 2: 270 degree shifted clock
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others => 0); -- 0: None
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-- pragma translate_off
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subtype tech_description is string(1 to 10);
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type tech_table_type is array (0 to NTECH) of tech_description;
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-------------------------------------------------------------------------------
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constant tech_table : tech_table_type := (
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inferred => "inferred ", virtex => "virtex ",
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virtex2 => "virtex2 ", memvirage => "virage ",
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axcel => "axcel ", proasic => "proasic ",
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atc18s => "atc18s ", altera => "altera ",
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umc => "umc18 ", rhumc => "rhumc ",
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apa3 => "proasic3 ", spartan3 => "spartan3 ",
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ihp25 => "ihp25 ", rhlib18t => "rhlib18t ",
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virtex4 => "virtex4 ", lattice => "lattice ",
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ut25 => "ut025crh ", spartan3e => "spartan3e ",
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peregrine => "peregrine ", memartisan => "artisan ",
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virtex5 => "virtex5 ", custom1 => "custom1 ",
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ihp25rh => "ihp25rh ", stratix1 => "stratix ",
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stratix2 => "stratixii ", eclipse => "eclipse ",
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stratix3 => "stratixiii", cyclone3 => "cycloneiii",
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memvirage90 => "virage90 ", tsmc90 => "tsmc90 ",
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easic90 => "nextreme ", atc18rha => "atc18rha ",
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smic013 => "smic13 ", tm65gpl => "tm65gplus ",
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axdsp => "axdsp ", spartan6 => "spartan6 ",
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virtex6 => "virtex6 ", actfus => "fusion ",
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stratix4 => "stratix4 ", st65lp => "st65lp ",
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st65gp => "st65gp ", easic45 => "nextreme2 ",
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cmos9sf => "cmos9sf ", apa3e => "proasic3e ",
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apa3l => "proasic3l ", ut130 => "ut130hbd ",
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ut90 => "ut90nhbd ");
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-- pragma translate_on
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-- input/output voltage
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constant x12v : integer := 12;
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constant x15v : integer := 15;
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constant x18v : integer := 1;
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constant x25v : integer := 2;
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constant x33v : integer := 3;
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constant x50v : integer := 5;
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-- input/output levels
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constant ttl : integer := 0;
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constant cmos : integer := 1;
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constant pci33 : integer := 2;
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constant pci66 : integer := 3;
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constant lvds : integer := 4;
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constant sstl2_i : integer := 5;
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constant sstl2_ii : integer := 6;
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constant sstl3_i : integer := 7;
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constant sstl3_ii : integer := 8;
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constant sstl18_i : integer := 9;
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constant sstl18_ii: integer := 10;
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constant lvpecl : integer := 11;
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-- pad types
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constant normal : integer := 0;
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constant pullup : integer := 1;
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constant pulldown : integer := 2;
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constant opendrain: integer := 3;
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constant schmitt : integer := 4;
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constant dci : integer := 5;
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---------------------------------------------------------------------------
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-- MEMORY
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---------------------------------------------------------------------------
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-- synchronous single-port ram
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component syncram
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generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
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testen : integer := 0);
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port (
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clk : in std_ulogic;
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address : in std_logic_vector((abits -1) downto 0);
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datain : in std_logic_vector((dbits -1) downto 0);
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dataout : out std_logic_vector((dbits -1) downto 0);
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enable : in std_ulogic;
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write : in std_ulogic;
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testin : in std_logic_vector(3 downto 0) := "0000");
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end component;
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-- synchronous two-port ram (1 read, 1 write port)
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component syncram_2p
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generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
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sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
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words : integer := 0);
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port (
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rclk : in std_ulogic;
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renable : in std_ulogic;
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raddress : in std_logic_vector((abits -1) downto 0);
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dataout : out std_logic_vector((dbits -1) downto 0);
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wclk : in std_ulogic;
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write : in std_ulogic;
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waddress : in std_logic_vector((abits -1) downto 0);
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datain : in std_logic_vector((dbits -1) downto 0);
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testin : in std_logic_vector(3 downto 0) := "0000");
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end component;
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-- synchronous dual-port ram (2 read/write ports)
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component syncram_dp
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generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
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testen : integer := 0);
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port (
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clk1 : in std_ulogic;
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address1 : in std_logic_vector((abits -1) downto 0);
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datain1 : in std_logic_vector((dbits -1) downto 0);
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dataout1 : out std_logic_vector((dbits -1) downto 0);
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enable1 : in std_ulogic;
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write1 : in std_ulogic;
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clk2 : in std_ulogic;
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|
address2 : in std_logic_vector((abits -1) downto 0);
|
|
|
datain2 : in std_logic_vector((dbits -1) downto 0);
|
|
|
dataout2 : out std_logic_vector((dbits -1) downto 0);
|
|
|
enable2 : in std_ulogic;
|
|
|
write2 : in std_ulogic;
|
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
|
|
end component;
|
|
|
|
|
|
-- synchronous 3-port regfile (2 read, 1 write port)
|
|
|
component regfile_3p
|
|
|
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
|
|
|
wrfst : integer := 0; numregs : integer := 64; testen : integer := 0);
|
|
|
port (
|
|
|
wclk : in std_ulogic;
|
|
|
waddr : in std_logic_vector((abits -1) downto 0);
|
|
|
wdata : in std_logic_vector((dbits -1) downto 0);
|
|
|
we : in std_ulogic;
|
|
|
rclk : in std_ulogic;
|
|
|
raddr1 : in std_logic_vector((abits -1) downto 0);
|
|
|
re1 : in std_ulogic;
|
|
|
rdata1 : out std_logic_vector((dbits -1) downto 0);
|
|
|
raddr2 : in std_logic_vector((abits -1) downto 0);
|
|
|
re2 : in std_ulogic;
|
|
|
rdata2 : out std_logic_vector((dbits -1) downto 0);
|
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
|
|
end component;
|
|
|
|
|
|
-- 64-bit synchronous single-port ram with 32-bit write strobe
|
|
|
component syncram64
|
|
|
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0);
|
|
|
port (
|
|
|
clk : in std_ulogic;
|
|
|
address : in std_logic_vector (abits -1 downto 0);
|
|
|
datain : in std_logic_vector (63 downto 0);
|
|
|
dataout : out std_logic_vector (63 downto 0);
|
|
|
enable : in std_logic_vector (1 downto 0);
|
|
|
write : in std_logic_vector (1 downto 0);
|
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
|
|
end component;
|
|
|
|
|
|
-- 128-bit synchronous single-port ram with 32-bit write strobe
|
|
|
component syncram128
|
|
|
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0);
|
|
|
port (
|
|
|
clk : in std_ulogic;
|
|
|
address : in std_logic_vector (abits -1 downto 0);
|
|
|
datain : in std_logic_vector (127 downto 0);
|
|
|
dataout : out std_logic_vector (127 downto 0);
|
|
|
enable : in std_logic_vector (3 downto 0);
|
|
|
write : in std_logic_vector (3 downto 0);
|
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
|
|
end component;
|
|
|
|
|
|
component syncramft
|
|
|
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
|
|
|
ft : integer range 0 to 3 := 0; testen : integer := 0 );
|
|
|
port (
|
|
|
clk : in std_ulogic;
|
|
|
address : in std_logic_vector((abits -1) downto 0);
|
|
|
datain : in std_logic_vector((dbits -1) downto 0);
|
|
|
dataout : out std_logic_vector((dbits -1) downto 0);
|
|
|
write : in std_ulogic;
|
|
|
enable : in std_ulogic;
|
|
|
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
|
|
|
testin : in std_logic_vector(3 downto 0) := "0000";
|
|
|
errinj : in std_logic_vector(((dbits + 7)/8)*2-1 downto 0) := (others => '0'));
|
|
|
end component;
|
|
|
|
|
|
component syncram_2pft
|
|
|
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
|
|
|
sepclk : integer := 0; wrfst : integer := 0; ft : integer := 0;
|
|
|
testen : integer := 0; words : integer := 0);
|
|
|
port (
|
|
|
rclk : in std_ulogic;
|
|
|
renable : in std_ulogic;
|
|
|
raddress : in std_logic_vector((abits -1) downto 0);
|
|
|
dataout : out std_logic_vector((dbits -1) downto 0);
|
|
|
wclk : in std_ulogic;
|
|
|
write : in std_ulogic;
|
|
|
waddress : in std_logic_vector((abits -1) downto 0);
|
|
|
datain : in std_logic_vector((dbits -1) downto 0);
|
|
|
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
|
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
|
|
end component;
|
|
|
|
|
|
component syncfifo
|
|
|
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
|
|
|
sepclk : integer := 0; wrfst : integer := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
rclk : in std_ulogic;
|
|
|
renable : in std_ulogic;
|
|
|
dataout : out std_logic_vector((dbits -1) downto 0);
|
|
|
wclk : in std_ulogic;
|
|
|
write : in std_ulogic;
|
|
|
datain : in std_logic_vector((dbits -1) downto 0);
|
|
|
full : out std_ulogic;
|
|
|
empty : out std_ulogic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component syncram128bw
|
|
|
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0);
|
|
|
port (
|
|
|
clk : in std_ulogic;
|
|
|
address : in std_logic_vector (abits -1 downto 0);
|
|
|
datain : in std_logic_vector (127 downto 0);
|
|
|
dataout : out std_logic_vector (127 downto 0);
|
|
|
enable : in std_logic_vector (15 downto 0);
|
|
|
write : in std_logic_vector (15 downto 0);
|
|
|
testin : in std_logic_vector (3 downto 0) := "0000");
|
|
|
end component;
|
|
|
|
|
|
component syncram156bw
|
|
|
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0);
|
|
|
port (
|
|
|
clk : in std_ulogic;
|
|
|
address : in std_logic_vector (abits -1 downto 0);
|
|
|
datain : in std_logic_vector (155 downto 0);
|
|
|
dataout : out std_logic_vector (155 downto 0);
|
|
|
enable : in std_logic_vector (15 downto 0);
|
|
|
write : in std_logic_vector (15 downto 0);
|
|
|
testin : in std_logic_vector (3 downto 0) := "0000");
|
|
|
end component;
|
|
|
|
|
|
component syncram256bw is
|
|
|
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0);
|
|
|
port (
|
|
|
clk : in std_ulogic;
|
|
|
address : in std_logic_vector (abits -1 downto 0);
|
|
|
datain : in std_logic_vector (255 downto 0);
|
|
|
dataout : out std_logic_vector (255 downto 0);
|
|
|
enable : in std_logic_vector (31 downto 0);
|
|
|
write : in std_logic_vector (31 downto 0);
|
|
|
testin : in std_logic_vector (3 downto 0) := "0000");
|
|
|
end component;
|
|
|
|
|
|
---------------------------------------------------------------------------
|
|
|
-- PADS
|
|
|
---------------------------------------------------------------------------
|
|
|
|
|
|
component inpad
|
|
|
generic (tech : integer := 0; level : integer := 0;
|
|
|
voltage : integer := x33v; filter : integer := 0;
|
|
|
strength : integer := 0);
|
|
|
port (pad : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component inpadv
|
|
|
generic (tech : integer := 0; level : integer := 0;
|
|
|
voltage : integer := x33v; width : integer := 1);
|
|
|
port (
|
|
|
pad : in std_logic_vector(width-1 downto 0);
|
|
|
o : out std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component iopad
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12;
|
|
|
oepol : integer := 0; filter : integer := 0);
|
|
|
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component iopadv
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (
|
|
|
pad : inout std_logic_vector(width-1 downto 0);
|
|
|
i : in std_logic_vector(width-1 downto 0);
|
|
|
en : in std_ulogic;
|
|
|
o : out std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component iopadvv is
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (
|
|
|
pad : inout std_logic_vector(width-1 downto 0);
|
|
|
i : in std_logic_vector(width-1 downto 0);
|
|
|
en : in std_logic_vector(width-1 downto 0);
|
|
|
o : out std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component iodpad
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12;
|
|
|
oepol : integer := 0);
|
|
|
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component iodpadv
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (
|
|
|
pad : inout std_logic_vector(width-1 downto 0);
|
|
|
i : in std_logic_vector(width-1 downto 0);
|
|
|
o : out std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component outpad
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12);
|
|
|
port (pad : out std_ulogic; i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component outpadv
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1);
|
|
|
port (
|
|
|
pad : out std_logic_vector(width-1 downto 0);
|
|
|
i : in std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component odpad
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12;
|
|
|
oepol : integer := 0);
|
|
|
port (pad : out std_ulogic; i : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component odpadv
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (
|
|
|
pad : out std_logic_vector(width-1 downto 0);
|
|
|
i : in std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component toutpad
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12;
|
|
|
oepol : integer := 0);
|
|
|
port (pad : out std_ulogic; i, en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component toutpadv
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (
|
|
|
pad : out std_logic_vector(width-1 downto 0);
|
|
|
i : in std_logic_vector(width-1 downto 0);
|
|
|
en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component toutpadvv is
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (
|
|
|
pad : out std_logic_vector(width-1 downto 0);
|
|
|
i : in std_logic_vector(width-1 downto 0);
|
|
|
en : in std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component toutpad_ds
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12;
|
|
|
oepol : integer := 0);
|
|
|
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component toutpad_dsv
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (
|
|
|
padp : out std_logic_vector(width-1 downto 0);
|
|
|
padn : out std_logic_vector(width-1 downto 0);
|
|
|
i : in std_logic_vector(width-1 downto 0);
|
|
|
en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component toutpad_dsvv is
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (
|
|
|
padp : out std_logic_vector(width-1 downto 0);
|
|
|
padn : out std_logic_vector(width-1 downto 0);
|
|
|
i : in std_logic_vector(width-1 downto 0);
|
|
|
en : in std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component skew_outpad
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
|
|
|
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
|
|
|
o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component clkpad
|
|
|
generic (tech : integer := 0; level : integer := 0;
|
|
|
voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
|
|
|
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component inpad_ds
|
|
|
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
|
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component clkpad_ds
|
|
|
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
|
|
|
port (padp, padn : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component inpad_dsv
|
|
|
generic (tech : integer := 0; level : integer := lvds;
|
|
|
voltage : integer := x33v; width : integer := 1; term : integer := 0);
|
|
|
port (
|
|
|
padp : in std_logic_vector(width-1 downto 0);
|
|
|
padn : in std_logic_vector(width-1 downto 0);
|
|
|
o : out std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component iopad_ds
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12;
|
|
|
oepol : integer := 0; term : integer := 0);
|
|
|
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component outpad_ds
|
|
|
generic (tech : integer := 0; level : integer := lvds;
|
|
|
voltage : integer := x33v; oepol : integer := 0);
|
|
|
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component outpad_dsv
|
|
|
generic (tech : integer := 0; level : integer := lvds;
|
|
|
voltage : integer := x33v; width : integer := 1);
|
|
|
port (
|
|
|
padp : out std_logic_vector(width-1 downto 0);
|
|
|
padn : out std_logic_vector(width-1 downto 0);
|
|
|
i, en: in std_logic_vector(width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
component lvds_combo is
|
|
|
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
|
|
|
oepol : integer := 0; term : integer := 0);
|
|
|
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
|
|
|
odval, osval, en : in std_logic_vector(0 to width-1);
|
|
|
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
|
|
|
idval, isval : out std_logic_vector(0 to width-1);
|
|
|
lvdsref : in std_logic := '1'
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
|
-- DDR PADS (bundles PAD and DDR register(s))
|
|
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
component inpad_ddr
|
|
|
generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v;
|
|
|
filter : integer := 0; strength : integer := 0 );
|
|
|
port (pad : in std_ulogic; o1, o2 : out std_ulogic; c1, c2 : in std_ulogic;
|
|
|
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component inpad_ddrv
|
|
|
generic (tech : integer := 0; level : integer := 0; voltage : integer := 0;
|
|
|
filter : integer := 0; strength : integer := 0; width : integer := 1);
|
|
|
port (pad : in std_logic_vector(width-1 downto 0);
|
|
|
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
|
|
|
ce : in std_ulogic; r: in std_ulogic; s : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component outpad_ddr
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12);
|
|
|
port (pad : out std_ulogic; i1, i2 : in std_ulogic; c1, c2 : in std_ulogic;
|
|
|
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component outpad_ddrv
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := 0; strength : integer := 12;
|
|
|
width : integer := 1);
|
|
|
port (pad : out std_logic_vector(width-1 downto 0);
|
|
|
i1, i2 : in std_logic_vector(width-1 downto 0);
|
|
|
c1, c2 : in std_ulogic; ce : in std_ulogic;
|
|
|
r : in std_ulogic; s : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component iopad_ddr
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12;
|
|
|
oepol : integer := 0);
|
|
|
port (pad : inout std_ulogic; i1, i2 : in std_ulogic; en : in std_ulogic;
|
|
|
o1, o2 : out std_ulogic; c1, c2 : in std_ulogic; ce : in std_ulogic;
|
|
|
r : in std_ulogic; s : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component iopad_ddrv
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (pad : inout std_logic_vector(width-1 downto 0);
|
|
|
i1, i2 : in std_logic_vector(width-1 downto 0); en : in std_ulogic;
|
|
|
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
|
|
|
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component iopad_ddrvv
|
|
|
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
|
|
|
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
|
|
|
oepol : integer := 0);
|
|
|
port (pad : inout std_logic_vector(width-1 downto 0);
|
|
|
i1, i2 : in std_logic_vector(width-1 downto 0);
|
|
|
en : in std_logic_vector(width-1 downto 0);
|
|
|
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
|
|
|
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
---------------------------------------------------------------------------
|
|
|
-- BUFFERS
|
|
|
---------------------------------------------------------------------------
|
|
|
|
|
|
component techbuf is
|
|
|
generic(
|
|
|
buftype : integer range 0 to 6 := 0;
|
|
|
tech : integer range 0 to NTECH := inferred);
|
|
|
port(
|
|
|
i : in std_ulogic;
|
|
|
o : out std_ulogic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
---------------------------------------------------------------------------
|
|
|
-- CLOCK GENERATION
|
|
|
---------------------------------------------------------------------------
|
|
|
|
|
|
type clkgen_in_type is record
|
|
|
pllref : std_logic; -- optional reference for PLL
|
|
|
pllrst : std_logic; -- optional reset for PLL
|
|
|
pllctrl : std_logic_vector(1 downto 0); -- optional control for PLL
|
|
|
clksel : std_logic_vector(1 downto 0); -- optional clock select
|
|
|
end record;
|
|
|
|
|
|
type clkgen_out_type is record
|
|
|
clklock : std_logic;
|
|
|
pcilock : std_logic;
|
|
|
end record;
|
|
|
|
|
|
component clkgen
|
|
|
generic (
|
|
|
tech : integer := DEFFABTECH;
|
|
|
clk_mul : integer := 1;
|
|
|
clk_div : integer := 1;
|
|
|
sdramen : integer := 0;
|
|
|
noclkfb : integer := 1;
|
|
|
pcien : integer := 0;
|
|
|
pcidll : integer := 0;
|
|
|
pcisysclk: integer := 0;
|
|
|
freq : integer := 25000;
|
|
|
clk2xen : integer := 0;
|
|
|
clksel : integer := 0; -- enable clock select
|
|
|
clk_odiv : integer := 1; -- Proasic3/Fusion output divider clkA
|
|
|
clkb_odiv: integer := 0; -- Proasic3/Fusion output divider clkB
|
|
|
clkc_odiv: integer := 0); -- Proasic3/Fusion output divider clkC
|
|
|
port (
|
|
|
clkin : in std_logic;
|
|
|
pciclkin: in std_logic;
|
|
|
clk : out std_logic; -- main clock
|
|
|
clkn : out std_logic; -- inverted main clock
|
|
|
clk2x : out std_logic; -- 2x clock
|
|
|
sdclk : out std_logic; -- SDRAM clock
|
|
|
pciclk : out std_logic; -- PCI clock
|
|
|
cgi : in clkgen_in_type;
|
|
|
cgo : out clkgen_out_type;
|
|
|
clk4x : out std_logic; -- 4x clock
|
|
|
clk1xu : out std_logic; -- unscaled 1X clock
|
|
|
clk2xu : out std_logic; -- unscaled 2X clock
|
|
|
clkb : out std_logic; -- Proasic3/Fusion clkB
|
|
|
clkc : out std_logic); -- Proasic3/Fusion clkC
|
|
|
end component;
|
|
|
|
|
|
component clkand
|
|
|
generic( tech : integer := 0;
|
|
|
ren : integer range 0 to 1 := 0); -- registered enable
|
|
|
port(
|
|
|
i : in std_ulogic;
|
|
|
en : in std_ulogic;
|
|
|
o : out std_ulogic;
|
|
|
tsten : in std_ulogic := '0'
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component clkmux
|
|
|
generic( tech : integer := 0;
|
|
|
rsel : integer range 0 to 1 := 0); -- registered sel
|
|
|
port(
|
|
|
i0, i1 : in std_ulogic;
|
|
|
sel : in std_ulogic;
|
|
|
o : out std_ulogic;
|
|
|
rst : in std_ulogic := '1'
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component clkrand is
|
|
|
generic( tech : integer := 0);
|
|
|
port(
|
|
|
i : in std_ulogic;
|
|
|
en : in std_ulogic;
|
|
|
o : out std_ulogic;
|
|
|
tsten : in std_ulogic := '0'
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------
|
|
|
-- TAP controller and boundary scan
|
|
|
---------------------------------------------------------------------------
|
|
|
|
|
|
component tap
|
|
|
generic (
|
|
|
tech : integer := 0;
|
|
|
irlen : integer range 2 to 8 := 4;
|
|
|
idcode : integer range 0 to 255 := 9;
|
|
|
manf : integer range 0 to 2047 := 804;
|
|
|
part : integer range 0 to 65535 := 0;
|
|
|
ver : integer range 0 to 15 := 0;
|
|
|
trsten : integer range 0 to 1 := 1;
|
|
|
scantest : integer := 0);
|
|
|
port (
|
|
|
trst : in std_ulogic;
|
|
|
tck : in std_ulogic;
|
|
|
tms : in std_ulogic;
|
|
|
tdi : in std_ulogic;
|
|
|
tdo : out std_ulogic;
|
|
|
tapo_tck : out std_ulogic;
|
|
|
tapo_tdi : out std_ulogic;
|
|
|
tapo_inst : out std_logic_vector(7 downto 0);
|
|
|
tapo_rst : out std_ulogic;
|
|
|
tapo_capt : out std_ulogic;
|
|
|
tapo_shft : out std_ulogic;
|
|
|
tapo_upd : out std_ulogic;
|
|
|
tapo_xsel1 : out std_ulogic;
|
|
|
tapo_xsel2 : out std_ulogic;
|
|
|
tapi_en1 : in std_ulogic;
|
|
|
tapi_tdo1 : in std_ulogic;
|
|
|
tapi_tdo2 : in std_ulogic;
|
|
|
testen : in std_ulogic := '0';
|
|
|
testrst : in std_ulogic := '1';
|
|
|
tdoen : out std_ulogic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component scanregi
|
|
|
generic (
|
|
|
tech : integer := 0
|
|
|
);
|
|
|
port (
|
|
|
pad : in std_ulogic;
|
|
|
core : out std_ulogic;
|
|
|
tck : in std_ulogic;
|
|
|
tdi : in std_ulogic;
|
|
|
tdo : out std_ulogic;
|
|
|
bsshft : in std_ulogic;
|
|
|
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
|
|
|
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
|
|
|
bsdrive : in std_ulogic; -- drive data reg to core
|
|
|
bshighz : in std_ulogic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component scanrego
|
|
|
generic (
|
|
|
tech : integer := 0
|
|
|
);
|
|
|
port (
|
|
|
pad : out std_ulogic;
|
|
|
core : in std_ulogic;
|
|
|
samp : in std_ulogic; -- normally same as core unless outpad has feedback
|
|
|
tck : in std_ulogic;
|
|
|
tdi : in std_ulogic;
|
|
|
tdo : out std_ulogic;
|
|
|
bsshft : in std_ulogic;
|
|
|
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
|
|
|
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
|
|
|
bsdrive : in std_ulogic -- drive data reg to pad
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component scanregio -- 3 scan registers: tdo<--input<--output<--outputen<--tdi
|
|
|
generic (
|
|
|
tech : integer := 0;
|
|
|
hzsup: integer range 0 to 1 := 1
|
|
|
);
|
|
|
port (
|
|
|
pado : out std_ulogic;
|
|
|
padoen : out std_ulogic;
|
|
|
padi : in std_ulogic;
|
|
|
coreo : in std_ulogic;
|
|
|
coreoen : in std_ulogic;
|
|
|
corei : out std_ulogic;
|
|
|
tck : in std_ulogic;
|
|
|
tdi : in std_ulogic;
|
|
|
tdo : out std_ulogic;
|
|
|
bsshft : in std_ulogic;
|
|
|
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
|
|
|
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
|
|
|
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
|
|
|
bsdrive : in std_ulogic; -- drive outdata regs to pad,
|
|
|
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
|
|
|
bshighz : in std_ulogic -- tri-state output
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
---------------------------------------------------------------------------
|
|
|
-- DDR registers and PHY
|
|
|
---------------------------------------------------------------------------
|
|
|
|
|
|
component ddr_ireg is
|
|
|
generic ( tech : integer);
|
|
|
port ( Q1 : out std_ulogic;
|
|
|
Q2 : out std_ulogic;
|
|
|
C1 : in std_ulogic;
|
|
|
C2 : in std_ulogic;
|
|
|
CE : in std_ulogic;
|
|
|
D : in std_ulogic;
|
|
|
R : in std_ulogic;
|
|
|
S : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ddr_oreg is generic ( tech : integer);
|
|
|
port
|
|
|
( Q : out std_ulogic;
|
|
|
C1 : in std_ulogic;
|
|
|
C2 : in std_ulogic;
|
|
|
CE : in std_ulogic;
|
|
|
D1 : in std_ulogic;
|
|
|
D2 : in std_ulogic;
|
|
|
R : in std_ulogic;
|
|
|
S : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component ddrphy
|
|
|
generic (tech : integer := virtex2; MHz : integer := 100;
|
|
|
rstdelay : integer := 200; dbits : integer := 16;
|
|
|
clk_mul : integer := 2 ; clk_div : integer := 2;
|
|
|
rskew : integer :=0; mobile : integer := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
clkread : out std_ulogic; -- read clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
|
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
|
|
ba : in std_logic_vector ( 1 downto 0); -- data mask
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0);
|
|
|
ck : in std_logic_vector(2 downto 0);
|
|
|
moben : in std_logic);
|
|
|
end component;
|
|
|
|
|
|
component ddr2phy
|
|
|
generic (
|
|
|
tech : integer := virtex5; MHz : integer := 100;
|
|
|
rstdelay : integer := 200; dbits : integer := 16;
|
|
|
clk_mul : integer := 2; clk_div : integer := 2;
|
|
|
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
|
|
|
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
|
|
|
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
|
|
|
cbdelayb0 : integer := 0;
|
|
|
cbdelayb1 : integer := 0; cbdelayb2: integer := 0; cbdelayb3: integer := 0;
|
|
|
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
|
|
|
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
|
|
|
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
|
|
|
cben : integer := 0; chkbits : integer := 8; ctrl2en: integer := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkref : in std_logic; -- input reference clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
|
|
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(ncs-1 downto 0);
|
|
|
|
|
|
addr : in std_logic_vector (abits-1 downto 0);
|
|
|
ba : in std_logic_vector ( 2 downto 0);
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(ncs-1 downto 0);
|
|
|
cke : in std_logic_vector(ncs-1 downto 0);
|
|
|
cal_en : in std_logic_vector(dbits/8-1 downto 0);
|
|
|
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
|
|
|
cal_pll : in std_logic_vector(1 downto 0);
|
|
|
cal_rst : in std_logic;
|
|
|
odt : in std_logic_vector(ncs-1 downto 0);
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oct : in std_logic;
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read_pend : in std_logic_vector(7 downto 0);
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regwdata : in std_logic_vector(63 downto 0);
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regwrite : in std_logic_vector(1 downto 0);
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regrdata : out std_logic_vector(63 downto 0);
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ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
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ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
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ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
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ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
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cbdqin : out std_logic_vector(chkbits*2-1 downto 0);
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cbdqout : in std_logic_vector(chkbits*2-1 downto 0);
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cbdm : in std_logic_vector(chkbits/4-1 downto 0);
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cbcal_en : in std_logic_vector(chkbits/8-1 downto 0);
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cbcal_inc : in std_logic_vector(chkbits/8-1 downto 0);
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|
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-- Copy of control signals for 2nd DIMM
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ddr_web2 : out std_ulogic; -- ddr write enable
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ddr_rasb2 : out std_ulogic; -- ddr ras
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ddr_casb2 : out std_ulogic; -- ddr cas
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ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
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ddr_ba2 : out std_logic_vector (1+eightbanks downto 0) -- ddr bank address
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|
);
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end component;
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|
|
|
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|
---------------------------------------------------------------------------
|
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|
-- 61x61 Multiplier
|
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---------------------------------------------------------------------------
|
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component mul_61x61
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generic (multech : integer := 0;
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fabtech : integer := 0);
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port(A : in std_logic_vector(60 downto 0);
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|
B : in std_logic_vector(60 downto 0);
|
|
|
EN : in std_logic;
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|
|
CLK : in std_logic;
|
|
|
PRODUCT : out std_logic_vector(121 downto 0));
|
|
|
end component;
|
|
|
|
|
|
---------------------------------------------------------------------------
|
|
|
-- Ring oscillator
|
|
|
---------------------------------------------------------------------------
|
|
|
|
|
|
component ringosc
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|
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generic (tech : integer := 0);
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|
|
port (
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|
|
roen : in Std_ULogic;
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|
|
roout : out Std_ULogic);
|
|
|
end component;
|
|
|
|
|
|
---------------------------------------------------------------------------
|
|
|
-- System monitor
|
|
|
---------------------------------------------------------------------------
|
|
|
|
|
|
component system_monitor
|
|
|
generic (
|
|
|
-- GRLIB generics
|
|
|
tech : integer := DEFFABTECH;
|
|
|
-- Virtex 5 SYSMON generics
|
|
|
INIT_40 : bit_vector := X"0000";
|
|
|
INIT_41 : bit_vector := X"0000";
|
|
|
INIT_42 : bit_vector := X"0800";
|
|
|
INIT_43 : bit_vector := X"0000";
|
|
|
INIT_44 : bit_vector := X"0000";
|
|
|
INIT_45 : bit_vector := X"0000";
|
|
|
INIT_46 : bit_vector := X"0000";
|
|
|
INIT_47 : bit_vector := X"0000";
|
|
|
INIT_48 : bit_vector := X"0000";
|
|
|
INIT_49 : bit_vector := X"0000";
|
|
|
INIT_4A : bit_vector := X"0000";
|
|
|
INIT_4B : bit_vector := X"0000";
|
|
|
INIT_4C : bit_vector := X"0000";
|
|
|
INIT_4D : bit_vector := X"0000";
|
|
|
INIT_4E : bit_vector := X"0000";
|
|
|
INIT_4F : bit_vector := X"0000";
|
|
|
INIT_50 : bit_vector := X"0000";
|
|
|
INIT_51 : bit_vector := X"0000";
|
|
|
INIT_52 : bit_vector := X"0000";
|
|
|
INIT_53 : bit_vector := X"0000";
|
|
|
INIT_54 : bit_vector := X"0000";
|
|
|
INIT_55 : bit_vector := X"0000";
|
|
|
INIT_56 : bit_vector := X"0000";
|
|
|
INIT_57 : bit_vector := X"0000";
|
|
|
SIM_MONITOR_FILE : string := "design.txt");
|
|
|
port (
|
|
|
alm : out std_logic_vector(2 downto 0);
|
|
|
busy : out std_ulogic;
|
|
|
channel : out std_logic_vector(4 downto 0);
|
|
|
do : out std_logic_vector(15 downto 0);
|
|
|
drdy : out std_ulogic;
|
|
|
eoc : out std_ulogic;
|
|
|
eos : out std_ulogic;
|
|
|
jtagbusy : out std_ulogic;
|
|
|
jtaglocked : out std_ulogic;
|
|
|
jtagmodified : out std_ulogic;
|
|
|
ot : out std_ulogic;
|
|
|
convst : in std_ulogic;
|
|
|
convstclk : in std_ulogic;
|
|
|
daddr : in std_logic_vector(6 downto 0);
|
|
|
dclk : in std_ulogic;
|
|
|
den : in std_ulogic;
|
|
|
di : in std_logic_vector(15 downto 0);
|
|
|
dwe : in std_ulogic;
|
|
|
reset : in std_ulogic;
|
|
|
vauxn : in std_logic_vector(15 downto 0);
|
|
|
vauxp : in std_logic_vector(15 downto 0);
|
|
|
vn : in std_ulogic;
|
|
|
vp : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
|
|
|
component nandtree
|
|
|
generic(
|
|
|
tech : integer := inferred;
|
|
|
width : integer := 2;
|
|
|
imp : integer := 0 );
|
|
|
port( i : in std_logic_vector(width-1 downto 0);
|
|
|
o : out std_ulogic;
|
|
|
en : in std_ulogic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component grmux2 is generic( tech : integer := inferred; imp : integer := 0);
|
|
|
port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end component;
|
|
|
|
|
|
component techmult
|
|
|
generic (
|
|
|
tech : integer := 0;
|
|
|
arch : integer := 0;
|
|
|
a_width : positive := 2; -- multiplier word width
|
|
|
b_width : positive := 2; -- multiplicand word width
|
|
|
num_stages : positive := 2; -- number of pipeline stages
|
|
|
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
|
|
|
);
|
|
|
port(a : in std_logic_vector(a_width-1 downto 0);
|
|
|
b : in std_logic_vector(b_width-1 downto 0);
|
|
|
clk : in std_logic;
|
|
|
en : in std_logic;
|
|
|
sign : in std_logic;
|
|
|
product : out std_logic_vector(a_width+b_width-1 downto 0));
|
|
|
end component;
|
|
|
|
|
|
end;
|
|
|
|
|
|
|
