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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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--! Programme qui permet de s�rialiser un vecteur
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entity Serialize is
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port(
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clk,raz : in std_logic; --! Horloge et Reset du composant
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sclk : in std_logic; --! Horloge Systeme
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vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entr�e
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send : in std_logic; --! Flag, Une nouvelle donn�e est pr�sente
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-- sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e
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Data : out std_logic --! Donn�e num�rique s�rialis�
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);
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end Serialize;
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architecture ar_Serialize of Serialize is
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type etat is (attente,serialize,reg);
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signal ect : etat;
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signal vector_int : std_logic_vector(16 downto 0);
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signal vectin_reg : std_logic_vector(15 downto 0);
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signal load : std_logic;
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signal N : integer range 0 to 16;
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signal CPT_ended : std_logic:='0';
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signal i : std_logic;
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begin
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process(clk,raz)
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begin
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if(raz='0')then
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ect <= attente;
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vectin_reg <= (others=> '0');
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load <= '0';
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i <= '1';
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-- sended <= '1';
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elsif(clk'event and clk='1')then
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vectin_reg <= vectin;
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case ect is
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when attente =>
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if (send='1') then
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-- sended <= '0';
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if(i='1')then
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i <= '0';
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ect <= reg;
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else
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load <= '1';
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ect <= serialize;
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end if;
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end if;
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when reg =>
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load <= '1';
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ect <= serialize;
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when serialize =>
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load <= '0';
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if(CPT_ended='1')then
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ect <= attente;
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-- sended <= '1';
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end if;
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end case;
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end if;
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end process;
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process(sclk,load,raz)
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begin
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if (raz='0')then
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vector_int <= (others=> '0');
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N <= 16;
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elsif(load='1')then
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vector_int <= vectin & '0';
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N <= 0;
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elsif(sclk'event and sclk='1')then
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if (CPT_ended='0') then
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vector_int <= vector_int(15 downto 0) & '0';
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N <= N+1;
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end if;
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end if;
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end process;
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CPT_ended <= '1' when N = 16 else '0';
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with ect select
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Data <= vector_int(16) when serialize,
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'0' when others;
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end ar_Serialize;
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