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include .config
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#GRLIB=$(GRLIB)
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TOP=BeagleSynth
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BOARD=BeagleSynth
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#BOARD=SP601
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include ../../boards/$(BOARD)/Makefile.inc
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DEVICE=$(PART)-$(PACKAGE)$(SPEED)
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#UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
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UCF=../../boards/$(BOARD)/default.ucf
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QSF=../../boards/$(BOARD)/$(TOP).qsf
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EFFORT=high
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ISEMAPOPT="-timing"
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XSTOPT=""
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SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
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VHDLOPTSYNFILES=
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VHDLSYNFILES= \
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config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd
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#VHDLSIMFILES=testbench.vhd
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#SIMTOP=testbench
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#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
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SDCFILE=default.sdc
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BITGEN=../../boards/$(BOARD)/default.ut
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CLEAN=soft-clean
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VCOMOPT=-explicit
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TECHLIBS = secureip unisim
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LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
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tmtc openchip cypress ihp gleichmann gsi fmf spansion
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DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
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leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
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ac97 hcan usb
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DIRADD =
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FILEADD =
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FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
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include $(GRLIB)/bin/Makefile
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include $(GRLIB)/software/leon3/Makefile
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################## project specific targets ##########################
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flash:
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xc3sprog -c ftdi -p 1 BeagleSynth.bit
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ram:
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xc3sprog -c ftdi -p 0 BeagleSynth.bit
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