HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/top_libero.prj.convert.8.1.bak

KEY LIBERO "8.1"

KEY CAPTURE "8.1.0.32"

KEY HDLTechnology "VHDL"

KEY VendorTechnology_Family "PROASIC3"

KEY VendorTechnology_Die "IT14X14M4LDP"

KEY VendorTechnology_Package "fg324"

KEY ProjectLocation "."

KEY SimulationType "VHDL"

KEY Vendor "Actel"

KEY ActiveRoot "top"

LIST REVISIONS

VALUE="Impl1",NUM=1

CURREV=1

ENDLIST

LIST LIBRARIES

grlib

proasic3

synplify

techmap

spw

eth

opencores

gaisler

esa

fmf

spansion

gsi

lpp

cypress

work

ENDLIST

LIST LIBRARIES_grlib

ALIAS=grlib

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_proasic3

ALIAS=proasic3

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_synplify

ALIAS=synplify

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_techmap

ALIAS=techmap

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_spw

ALIAS=spw

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_eth

ALIAS=eth

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_opencores

ALIAS=opencores

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_gaisler

ALIAS=gaisler

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_esa

ALIAS=esa

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_fmf

ALIAS=fmf

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_spansion

ALIAS=spansion

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_gsi

ALIAS=gsi

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_lpp

ALIAS=lpp

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_cypress

ALIAS=cypress

COMPILE_OPTION=COMPILE

ENDLIST

LIST LIBRARIES_work

ALIAS=work

COMPILE_OPTION=COMPILE

ENDLIST

LIST FileManager

VALUE "<project>/../..//lib/grlib/stdlib/version.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/stdlib/stdlib.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/stdlib/stdio.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/util/util.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/sparc/sparc.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/sparc/sparc_disas.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/sparc/cpu_disas.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/modgen/multlib.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/modgen/leaves.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/amba/amba.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/amba/devices.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/amba/defmst.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/amba/apbctrl.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/amba/ahbctrl.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/amba/dma2ahb_pkg.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/amba/dma2ahb.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/grlib/amba/dma2ahb_tp.vhd,hdl"

STATE="utd"

LIBRARY="grlib"

ENDFILE

VALUE "<project>/../..//lib/tech/proasic3/components/proasic3.vhd,hdl"

STATE="utd"

LIBRARY="proasic3"

ENDFILE

VALUE "<project>/../..//lib/synplify/sim/synplify.vhd,hdl"

STATE="utd"

LIBRARY="synplify"

ENDFILE

VALUE "<project>/../..//lib/synplify/sim/synattr.vhd,hdl"

STATE="utd"

LIBRARY="synplify"

ENDFILE

VALUE "<project>/../..//lib/techmap/gencomp/gencomp.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/gencomp/netcomp.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/inferred/memory_inferred.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/inferred/ddr_inferred.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/inferred/mul_inferred.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/proasic3/memory_apa3.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/proasic3/buffer_apa3.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/proasic3/tap_proasic3.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/allclkgen.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/allddr.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/allmem.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/allpads.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/alltap.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/clkgen.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/clkmux.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/clkand.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/ddr_ireg.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/ddr_oreg.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/ddrphy.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/syncram.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/syncram64.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/syncram_2p.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/syncram_dp.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/syncfifo.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/regfile_3p.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/tap.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/techbuf.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/clkpad.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/clkpad_ds.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/inpad.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/inpad_ds.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/iodpad.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/iopad.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/iopad_ds.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/lvds_combo.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/odpad.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/outpad.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/outpad_ds.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/toutpad.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/skew_outpad.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/grspwc_net.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/grlfpw_net.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/grfpw_net.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/mul_61x61.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/cpu_disas_net.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/usbhc_net.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/ringosc.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/techmap/maps/ssrctrl_net.vhd,hdl"

STATE="utd"

LIBRARY="techmap"

ENDFILE

VALUE "<project>/../..//lib/spw/comp/spwcomp.vhd,hdl"

STATE="utd"

LIBRARY="spw"

ENDFILE

VALUE "<project>/../..//lib/eth/comp/ethcomp.vhd,hdl"

STATE="utd"

LIBRARY="eth"

ENDFILE

VALUE "<project>/../..//lib/eth/core/greth_pkg.vhd,hdl"

STATE="utd"

LIBRARY="eth"

ENDFILE

VALUE "<project>/../..//lib/eth/core/eth_rstgen.vhd,hdl"

STATE="utd"

LIBRARY="eth"

ENDFILE

VALUE "<project>/../..//lib/eth/core/eth_ahb_mst.vhd,hdl"

STATE="utd"

LIBRARY="eth"

ENDFILE

VALUE "<project>/../..//lib/eth/core/greth_tx.vhd,hdl"

STATE="utd"

LIBRARY="eth"

ENDFILE

VALUE "<project>/../..//lib/eth/core/greth_rx.vhd,hdl"

STATE="utd"

LIBRARY="eth"

ENDFILE

VALUE "<project>/../..//lib/eth/core/grethc.vhd,hdl"

STATE="utd"

LIBRARY="eth"

ENDFILE

VALUE "<project>/../..//lib/eth/wrapper/greth_gen.vhd,hdl"

STATE="utd"

LIBRARY="eth"

ENDFILE

VALUE "<project>/../..//lib/eth/wrapper/greth_gbit_gen.vhd,hdl"

STATE="utd"

LIBRARY="eth"

ENDFILE

VALUE "<project>/../..//lib/opencores/occomp/occomp.vhd,hdl"

STATE="utd"

LIBRARY="opencores"

ENDFILE

VALUE "<project>/../..//lib/opencores/can/cancomp.vhd,hdl"

STATE="utd"

LIBRARY="opencores"

ENDFILE

VALUE "<project>/../..//lib/opencores/can/can_top.vhd,hdl"

STATE="utd"

LIBRARY="opencores"

ENDFILE

VALUE "<project>/../..//lib/opencores/can/can_top_core_sync.vhd,hdl"

STATE="utd"

LIBRARY="opencores"

ENDFILE

VALUE "<project>/../..//lib/gaisler/arith/arith.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

ENDFILE

VALUE "<project>/../..//lib/gaisler/arith/mul32.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

ENDFILE

VALUE "<project>/../..//lib/gaisler/arith/div32.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/memctrl/memctrl.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/memctrl/sdctrl.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/memctrl/sdmctrl.vhd,hdl"

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LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/memctrl/srctrl.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/leon3/leon3.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/leon3/mmuconfig.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/leon3/mmuiface.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/leon3/libmmu.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/leon3/libiu.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/leon3/libcache.vhd,hdl"

STATE="utd"

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VALUE "<project>/../..//lib/gaisler/leon3/libproc3.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/leon3/cachemem.vhd,hdl"

STATE="utd"

LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/leon3/mmu_icache.vhd,hdl"

STATE="utd"

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VALUE "<project>/../..//lib/gaisler/leon3/mmu_dcache.vhd,hdl"

STATE="utd"

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VALUE "<project>/../..//lib/gaisler/leon3/mmu_acache.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/mmutlbcam.vhd,hdl"

STATE="utd"

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VALUE "<project>/../..//lib/gaisler/leon3/mmulrue.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/mmulru.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/mmutlb.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/mmutw.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/mmu.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/mmu_cache.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/acache.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/dcache.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/icache.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/cache.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/cpu_disasx.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/iu3.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/grfpwx.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/mfpwx.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/grlfpwx.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/leon3/tbufmem.vhd,hdl"

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LIBRARY="gaisler"

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LIBRARY="gaisler"

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VALUE "<project>/../..//lib/gaisler/jtag/ahbjtag.vhd,hdl"

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VALUE "<project>/../..//lib/gaisler/jtag/ahbjtag_bsd.vhd,hdl"

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LIBRARY="gaisler"

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STATE="utd"

LIBRARY="gaisler"

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LIBRARY="gaisler"

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LIBRARY="lpp"

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VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"

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ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"

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ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"

STATE="utd"

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VALUE "<project>/../..//lib/lpp/./lpp_memory/ApbDriver.vhd,hdl"

STATE="utd"

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ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"

STATE="utd"

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ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_uart/APB_UART.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_uart/BaudGen.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_uart/UART.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_usb/APB_USB.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_usb/RWbuf.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"

STATE="utd"

LIBRARY="lpp"

ENDFILE

VALUE "<project>/../..//lib/cypress/ssram/components.vhd,hdl"

STATE="utd"

LIBRARY="cypress"

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VALUE "<project>/../..//lib/cypress/ssram/package_utility.vhd,hdl"

STATE="utd"

LIBRARY="cypress"

ENDFILE

VALUE "<project>/../..//lib/cypress/ssram/cy7c1354b.vhd,hdl"

STATE="utd"

LIBRARY="cypress"

ENDFILE

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STATE="utd"

LIBRARY="cypress"

ENDFILE

VALUE "<project>/../..//lib/work/debug/debug.vhd,hdl"

STATE="utd"

LIBRARY="work"

ENDFILE

VALUE "<project>/../..//lib/work/debug/grtestmod.vhd,hdl"

STATE="utd"

LIBRARY="work"

ENDFILE

VALUE "<project>/../..//lib/work/debug/cpu_disas.vhd,hdl"

STATE="utd"

LIBRARY="work"

ENDFILE

VALUE "<project>/config.vhd,hdl"

STATE="utd"

LIBRARY="work"

ENDFILE

VALUE "<project>/ahbrom.vhd,hdl"

STATE="utd"

LIBRARY="work"

ENDFILE

VALUE "<project>/leon3mp.vhd,hdl"

STATE="utd"

LIBRARY="work"

ENDFILE

VALUE "<project>/testbench.vhd,hdl"

STATE="utd"

LIBRARY="work"

ENDFILE

VALUE "<project>/../..//boards/TEST-LEON-M7-LPP/TEST-LEON-M7-LPP.pdc,pdc"

STATE="utd"

ENDFILE

ENDLIST

LIST SimulationOptions

ENDLIST

LIST ExcludePackageForSimulation

LIST top

ENDLIST

LIST ExcludePackageForSynthesis

LIST top

VALUE "<project>/../..//lib/grlib/stdlib/stdio.vhd,hdl"

VALUE "<project>/../..//lib/grlib/util/util.vhd,hdl"

VALUE "<project>/../..//lib/grlib/sparc/sparc_disas.vhd,hdl"

VALUE "<project>/../..//lib/grlib/sparc/cpu_disas.vhd,hdl"

VALUE "<project>/../..//lib/grlib/amba/dma2ahb_tp.vhd,hdl"

VALUE "<project>/../..//lib/tech/proasic3/components/proasic3.vhd,hdl"

VALUE "<project>/../..//lib/synplify/sim/synplify.vhd,hdl"

VALUE "<project>/../..//lib/synplify/sim/synattr.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/ambatest/ambatest.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/ambatest/ahb_tbfunct.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/ambatest/ahbslv_em.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/ambatest/ahbmst_em.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/sim/i2c_slave_model.v,hdl"

VALUE "<project>/../..//lib/gaisler/sim/sim.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/sim/sram.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/sim/ata_device.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/sim/sram16.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/sim/phy.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/sim/ahbrep.vhd,hdl"

VALUE "<project>/../..//lib/gaisler/jtag/jtagtst.vhd,hdl"

VALUE "<project>/../..//lib/fmf/utilities/conversions.vhd,hdl"

VALUE "<project>/../..//lib/fmf/utilities/gen_utils.vhd,hdl"

VALUE "<project>/../..//lib/gsi/ssram/functions.vhd,hdl"

VALUE "<project>/../..//lib/gsi/ssram/core_burst.vhd,hdl"

VALUE "<project>/../..//lib/gsi/ssram/g880e18bt.vhd,hdl"

VALUE "<project>/../..//lib/cypress/ssram/components.vhd,hdl"

VALUE "<project>/../..//lib/cypress/ssram/package_utility.vhd,hdl"

VALUE "<project>/../..//lib/cypress/ssram/cy7c1354b.vhd,hdl"

VALUE "<project>/../..//lib/cypress/ssram/cy7c1380d.vhd,hdl"

VALUE "<project>/../..//lib/work/debug/debug.vhd,hdl"

VALUE "<project>/../..//lib/work/debug/grtestmod.vhd,hdl"

VALUE "<project>/../..//lib/work/debug/cpu_disas.vhd,hdl"

VALUE "<project>/config.vhd,hdl"

VALUE "<project>/ahbrom.vhd,hdl"

VALUE "<project>/leon3mp.vhd,hdl"

VALUE "<project>/testbench.vhd,hdl"

ENDLIST

LIST IncludeModuleForSimulation

ENDLIST

LIST UserCustomizedFileList

LIST "top"

LIST "ideSYNTHESIS"

USE_LIST=TRUE

FILELIST