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--***************************************************************************************
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--
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-- File Name: CY7C1360C.vhd
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-- Version: 1.0
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-- Date: Aug 8th, 2005
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-- Model: BUS Functional
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-- Simulator: Modelsim
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--
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--
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-- Queries: MPD Applications
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-- Website: www.cypress.com/support
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-- Company: Cypress Semiconductor
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-- Part #: CY7C1360C (256K x 36)
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--
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-- Description: Cypress 9Mb Synburst SRAM (Pipelined SCD)
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--
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--
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-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
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-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
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-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
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-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
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--
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-- Copyright(c) Cypress Semiconductor, 2004
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-- All rights reserved
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--
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-- Rev Date Changes
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-- --- ---------- ---------------------------------------
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-- 1.0 12/22/2004 - New Model
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-- - New Test Bench
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-- - New Test Vectors
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--
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--***************************************************************************************
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-- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
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LIBRARY ieee,work;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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Use IEEE.Std_Logic_Arith.all;
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USE work.package_utility.all;
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entity CY7C1360C is
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GENERIC (
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-- Constant Parameters
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addr_bits : INTEGER := 18; -- This is external address
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data_bits : INTEGER := 36;
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--Clock timings for 250Mhz
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Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise
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Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
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Cyp_tCH : TIME := 1.8 ns; -- Clock HIGH time
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Cyp_tCL : TIME := 1.8 ns; -- Clock LOW time
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Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z
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Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z
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Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z
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Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
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Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid
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Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise
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Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
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Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise
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Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
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Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise
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Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up
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Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise
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Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise
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Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise
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Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
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Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise
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Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise
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--Clock timings for 200Mhz
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-- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise
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-- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time
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-- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time
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-- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time
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-- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z
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-- Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z
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-- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z
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-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
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-- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid
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-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
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-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
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-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
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-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
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-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
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-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
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-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
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-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
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-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
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-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
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-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
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-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
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--Clock timings for 166Mhz
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-- Cyp_tCO : TIME := 3.5 ns; -- Data Output Valid After CLK Rise
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-- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time
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-- Cyp_tCH : TIME := 2.4 ns; -- Clock HIGH time
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-- Cyp_tCL : TIME := 2.4 ns; -- Clock LOW time
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-- Cyp_tCHZ : TIME := 3.5 ns; -- Clock to High-Z
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-- Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z
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-- Cyp_tOEHZ: TIME := 3.5 ns; -- OE# HIGH to Output High-Z
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-- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z
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-- Cyp_tOEV : TIME := 3.5 ns; -- OE# LOW to Output Valid
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-- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise
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-- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
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-- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise
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-- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
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-- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise
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-- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up
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-- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise
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-- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise
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-- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise
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-- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
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-- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise
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-- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise
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);
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PORT (iZZ : IN STD_LOGIC;
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iMode : IN STD_LOGIC;
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iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
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inGW : IN STD_LOGIC;
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inBWE : IN STD_LOGIC;
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inBWd : IN STD_LOGIC;
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inBWc : IN STD_LOGIC;
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inBWb : IN STD_LOGIC;
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inBWa : IN STD_LOGIC;
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inCE1 : IN STD_LOGIC;
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iCE2 : IN STD_LOGIC;
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inCE3 : IN STD_LOGIC;
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inADSP : IN STD_LOGIC;
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inADSC : IN STD_LOGIC;
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inADV : IN STD_LOGIC;
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inOE : IN STD_LOGIC;
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ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
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iCLK : IN STD_LOGIC);
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end CY7C1360C;
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ARCHITECTURE CY7C1360C_arch OF CY7C1360C IS
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signal Read_reg_o1, Read_reg1 : STD_LOGIC;
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signal WrN_reg1 : STD_LOGIC;
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signal ADSP_N_o : STD_LOGIC;
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signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC;
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signal Sys_clk : STD_LOGIC := '0';
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signal test : STD_LOGIC;
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signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0);
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signal ce : STD_LOGIC;
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signal Write_n : STD_LOGIC;
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signal Read : STD_LOGIC;
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signal bwa_n1 : STD_LOGIC;
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signal bwb_n1 : STD_LOGIC;
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signal bwc_n1 : STD_LOGIC;
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signal bwd_n1 : STD_LOGIC;
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signal latch_addr : STD_LOGIC;
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signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0);
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signal OeN_HZ : STD_LOGIC;
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signal OeN_DataValid : STD_LOGIC;
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signal OeN_efct : STD_LOGIC;
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signal WR_HZ : STD_LOGIC;
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signal WR_LZ : STD_LOGIC;
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signal WR_efct : STD_LOGIC;
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signal CE_HZ : STD_LOGIC;
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signal CE_LZ : STD_LOGIC;
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signal Pipe_efct : STD_LOGIC;
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signal RD_HZ : STD_LOGIC;
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signal RD_LZ : STD_LOGIC;
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signal RD_efct : STD_LOGIC;
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begin
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ce <= ((not inCE1) and (iCE2) and (not inCE3));
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Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW));
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Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce));
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bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa))));
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bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb))));
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bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc))));
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bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd))));
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latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1)));
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OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ;
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WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ;
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Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ;
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RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ;
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Process (Read_reg_o1)
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begin
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if (Read_reg_o1 = '0') then
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RD_HZ <= '0' after Cyp_tCHZ;
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RD_LZ <= '0' after Cyp_tCLZ;
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elsif (Read_reg_o1 = '1') then
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RD_HZ <= '1' after Cyp_tCHZ;
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RD_LZ <= '1' after Cyp_tCLZ;
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else
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RD_HZ <= 'X' after Cyp_tCHZ;
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RD_LZ <= 'X' after Cyp_tCLZ;
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end if;
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end process;
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Process (pipe_reg1)
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begin
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if (pipe_reg1 = '1') then
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CE_LZ <= '1' after Cyp_tCLZ;
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elsif (pipe_reg1 = '0') then
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CE_LZ <= '0' after Cyp_tCLZ;
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else
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CE_LZ <= 'X' after Cyp_tCLZ;
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end if;
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end process;
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-- System Clock Decode
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Process (iclk)
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variable Sys_clk1 : std_logic := '0';
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begin
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if (rising_edge (iclk)) then
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Sys_clk1 := not iZZ;
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end if;
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if (falling_edge (iCLK)) then
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Sys_clk1 := '0';
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end if;
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Sys_clk <= Sys_clk1;
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end process;
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Process (WrN_reg1)
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begin
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if (WrN_reg1 = '1') then
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WR_HZ <= '1' after Cyp_tCHZ;
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WR_LZ <= '1' after Cyp_tCLZ;
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elsif (WrN_reg1 = '0') then
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WR_HZ <= '0' after Cyp_tCHZ;
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WR_LZ <= '0' after Cyp_tCLZ;
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else
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WR_HZ <= 'X' after Cyp_tCHZ;
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WR_LZ <= 'X' after Cyp_tCLZ;
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end if;
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end process;
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Process (inOE)
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begin
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if (inOE = '1') then
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OeN_HZ <= '1' after Cyp_tOEHZ;
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OeN_DataValid <= '1' after Cyp_tOEV;
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elsif (inOE = '0') then
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OeN_HZ <= '0' after Cyp_tOEHZ;
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OeN_DataValid <= '0' after Cyp_tOEV;
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else
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OeN_HZ <= 'X' after Cyp_tOEHZ;
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OeN_DataValid <= 'X' after Cyp_tOEV;
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end if;
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end process;
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process (ce_reg1, pipe_reg1)
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begin
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if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then
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CE_HZ <= '0' after Cyp_tCHZ;
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elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then
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CE_HZ <= '1' after Cyp_tCHZ;
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else
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CE_HZ <= 'X' after Cyp_tCHZ;
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end if;
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end process;
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Process (Sys_clk)
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TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0);
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variable Read_reg_o : std_logic;
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variable Read_reg : std_logic;
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variable pcsr_write, ctlr_write : std_logic;
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variable WrN_reg : std_logic;
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variable latch_addr_old, latch_addr_current : std_logic;
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variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0');
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variable bcount, first_addr : std_logic_vector (1 downto 0) := "00";
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variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic;
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variable din : std_logic_vector (data_bits-1 downto 0);
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variable first_addr_int : integer;
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variable bank0 : memory_array;
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variable bank1 : memory_array;
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variable bank2 : memory_array;
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variable bank3 : memory_array;
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begin
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if rising_edge (Sys_clk) then
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if (Write_n = '0') then
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Read_reg_o := '0';
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else
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Read_reg_o := Read_reg;
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end if;
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if (Write_n = '0') then
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Read_reg := '0';
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else
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Read_reg := Read;
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end if;
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Read_reg1 <= Read_reg;
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Read_reg_o1 <= Read_reg_o;
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if (Read_reg = '1') then
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pcsr_write := '0';
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ctlr_write := '0';
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end if;
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-- Write Register
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if (Read_reg_o = '1') then
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WrN_reg := '1';
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else
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WrN_reg := Write_n;
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end if;
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WrN_reg1 <= WrN_reg;
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latch_addr_old := latch_addr_current;
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latch_addr_current := latch_addr;
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if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then
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pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
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elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then
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ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1;
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end if;
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-- ADDRess Register
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if (latch_addr = '1') then
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addr_reg_in := iADDR;
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bcount := iADDR (1 downto 0);
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first_addr := iADDR (1 downto 0);
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end if;
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addr_reg_in1 <= addr_reg_in;
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-- ADSP_N Previous-Cycle Register
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ADSP_N_o <= inADSP;
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pcsr_write1 <= pcsr_write;
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ctlr_write1 <= ctlr_write;
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first_addr_int := CONV_INTEGER1 (first_addr);
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-- Binary Counter and Logic
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if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst
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bcount := (bcount + '1'); -- Advance Counter
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elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst
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if ((first_addr_int REM 2) = 0) then
|
|
|
bcount := (bcount + '1'); -- Increment Counter
|
|
|
elsif ((first_addr_int REM 2) = 1) then
|
|
|
bcount := (bcount - '1'); -- Decrement Counter
|
|
|
end if;
|
|
|
end if;
|
|
|
|
|
|
-- Read ADDRess
|
|
|
addr_reg_read := addr_reg_write;
|
|
|
addr_reg_read1 <= addr_reg_read;
|
|
|
|
|
|
-- Write ADDRess
|
|
|
addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0);
|
|
|
addr_reg_write1 <= addr_reg_write;
|
|
|
-- Byte Write Register
|
|
|
bwa_reg := not bwa_n1;
|
|
|
bwb_reg := not bwb_n1;
|
|
|
bwc_reg := not bwc_n1;
|
|
|
bwd_reg := not bwd_n1;
|
|
|
|
|
|
-- Enable Register
|
|
|
pipe_reg := ce_reg;
|
|
|
|
|
|
-- Enable Register
|
|
|
if (latch_addr = '1') then
|
|
|
ce_reg := ce;
|
|
|
end if;
|
|
|
|
|
|
pipe_reg1 <= pipe_reg;
|
|
|
ce_reg1 <= ce_reg;
|
|
|
|
|
|
-- Input Register
|
|
|
if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and
|
|
|
((pcsr_write = '1') or (ctlr_write = '1'))) then
|
|
|
din := ioDQ;
|
|
|
end if;
|
|
|
din1 <= din;
|
|
|
|
|
|
-- Byte Write Driver
|
|
|
if ((ce_reg = '1') and (bwa_reg = '1')) then
|
|
|
bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0);
|
|
|
end if;
|
|
|
if ((ce_reg = '1') and (bwb_reg = '1')) then
|
|
|
bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9);
|
|
|
end if;
|
|
|
if ((ce_reg = '1') and (bwc_reg = '1')) then
|
|
|
bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18);
|
|
|
end if;
|
|
|
if ((ce_reg = '1') and (bwd_reg = '1')) then
|
|
|
bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27);
|
|
|
end if;
|
|
|
|
|
|
-- Output Registers
|
|
|
|
|
|
if ((Write_n = '0') or (pipe_reg = '0')) then
|
|
|
dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ;
|
|
|
elsif (Read_reg_o = '1') then
|
|
|
dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
|
|
|
dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
|
|
|
dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
|
|
|
dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO;
|
|
|
end if;
|
|
|
|
|
|
end if;
|
|
|
end process;
|
|
|
|
|
|
-- Output Buffers
|
|
|
ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1'))
|
|
|
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
|
|
|
|
|
|
|
|
|
clk_check : PROCESS
|
|
|
VARIABLE clk_high, clk_low : TIME := 0 ns;
|
|
|
BEGIN
|
|
|
WAIT ON iClk;
|
|
|
IF iClk = '1' AND NOW >= Cyp_tCYC THEN
|
|
|
ASSERT (NOW - clk_low >= Cyp_tCH)
|
|
|
REPORT "Clk width low - tCH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (NOW - clk_high >= Cyp_tCYC)
|
|
|
REPORT "Clk period high - tCYC violation"
|
|
|
SEVERITY ERROR;
|
|
|
clk_high := NOW;
|
|
|
ELSIF iClk = '0' AND NOW /= 0 ns THEN
|
|
|
ASSERT (NOW - clk_high >= Cyp_tCL)
|
|
|
REPORT "Clk width high - tCL violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (NOW - clk_low >= Cyp_tCYC)
|
|
|
REPORT "Clk period low - tCYC violation"
|
|
|
SEVERITY ERROR;
|
|
|
clk_low := NOW;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
-- Check for Setup Timing Violation
|
|
|
setup_check : PROCESS
|
|
|
BEGIN
|
|
|
WAIT ON iClk;
|
|
|
IF iClk = '1' THEN
|
|
|
ASSERT (iAddr'LAST_EVENT >= Cyp_tAS)
|
|
|
REPORT "Addr - tAS violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inGW'LAST_EVENT >= Cyp_tWES)
|
|
|
REPORT "GW# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inBWE'LAST_EVENT >= Cyp_tWES)
|
|
|
REPORT "BWE# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inCe1'LAST_EVENT >= Cyp_tWES)
|
|
|
REPORT "CE1# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (iCe2'LAST_EVENT >= Cyp_tWES)
|
|
|
REPORT "CE2 - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inCe3'LAST_EVENT >= Cyp_tWES)
|
|
|
REPORT "CE3# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS)
|
|
|
REPORT "ADV# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS)
|
|
|
REPORT "ADSP# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS)
|
|
|
REPORT "ADSC# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inBwa'LAST_EVENT >= Cyp_tWES)
|
|
|
REPORT "BWa# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inBwb'LAST_EVENT >= Cyp_tWES)
|
|
|
REPORT "BWb# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inBwc'LAST_EVENT >= Cyp_tWES)
|
|
|
REPORT "BWc# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inBwd'LAST_EVENT >= Cyp_tWES)
|
|
|
REPORT "BWd# - tWES violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (ioDq'LAST_EVENT >= Cyp_tDS)
|
|
|
REPORT "Dq - tDS violation"
|
|
|
SEVERITY ERROR;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
-- Check for Hold Timing Violation
|
|
|
hold_check : PROCESS
|
|
|
BEGIN
|
|
|
WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH);
|
|
|
IF iClk'DELAYED(Cyp_tAH) = '1' THEN
|
|
|
ASSERT (iAddr'LAST_EVENT > Cyp_tAH)
|
|
|
REPORT "Addr - tAH violation"
|
|
|
SEVERITY ERROR;
|
|
|
END IF;
|
|
|
IF iClk'DELAYED(Cyp_tDH) = '1' THEN
|
|
|
ASSERT (ioDq'LAST_EVENT > Cyp_tDH)
|
|
|
REPORT "Dq - tDH violation"
|
|
|
SEVERITY ERROR;
|
|
|
END IF;
|
|
|
IF iClk'DELAYED(Cyp_tWEH) = '1' THEN
|
|
|
ASSERT (inCe1'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "CE1# - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (iCe2'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "CE2 - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inCe3'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "CE3 - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inAdv'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "ADV# - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inADSP'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "ADSP# - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inADSC'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "ADSC# - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inBwa'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "BWa# - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inBwb'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "BWb# - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inBwc'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "BWc# - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
ASSERT (inBwd'LAST_EVENT > Cyp_tWEH)
|
|
|
REPORT "BWd# - tWEH violation"
|
|
|
SEVERITY ERROR;
|
|
|
END IF;
|
|
|
|
|
|
END PROCESS;
|
|
|
end CY7C1360C_arch;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
