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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY gaisler;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.spacewire.ALL; -- PLE
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_lfr_time_management.ALL;
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USE lpp.lpp_leon3_soc_pkg.ALL;
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ENTITY MINI_LFR_top IS
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PORT (
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clk_50 : IN STD_LOGIC;
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clk_49 : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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--BPs
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BP0 : IN STD_LOGIC;
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BP1 : IN STD_LOGIC;
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--LEDs
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LED0 : OUT STD_LOGIC;
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LED1 : OUT STD_LOGIC;
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LED2 : OUT STD_LOGIC;
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--UARTs
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TXD1 : IN STD_LOGIC;
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RXD1 : OUT STD_LOGIC;
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nCTS1 : OUT STD_LOGIC;
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nRTS1 : IN STD_LOGIC;
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TXD2 : IN STD_LOGIC;
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RXD2 : OUT STD_LOGIC;
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nCTS2 : OUT STD_LOGIC;
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nDTR2 : IN STD_LOGIC;
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nRTS2 : IN STD_LOGIC;
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nDCD2 : OUT STD_LOGIC;
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--EXT CONNECTOR
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IO0 : INOUT STD_LOGIC;
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IO1 : INOUT STD_LOGIC;
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IO2 : INOUT STD_LOGIC;
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IO3 : INOUT STD_LOGIC;
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IO4 : INOUT STD_LOGIC;
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IO5 : INOUT STD_LOGIC;
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IO6 : INOUT STD_LOGIC;
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IO7 : INOUT STD_LOGIC;
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IO8 : INOUT STD_LOGIC;
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IO9 : INOUT STD_LOGIC;
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IO10 : INOUT STD_LOGIC;
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IO11 : INOUT STD_LOGIC;
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--SPACE WIRE
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SPW_EN : OUT STD_LOGIC; -- 0 => off
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SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
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SPW_NOM_SIN : IN STD_LOGIC;
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SPW_NOM_DOUT : OUT STD_LOGIC;
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SPW_NOM_SOUT : OUT STD_LOGIC;
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SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
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SPW_RED_SIN : IN STD_LOGIC;
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SPW_RED_DOUT : OUT STD_LOGIC;
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SPW_RED_SOUT : OUT STD_LOGIC;
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-- MINI LFR ADC INPUTS
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ADC_nCS : OUT STD_LOGIC;
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ADC_CLK : OUT STD_LOGIC;
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ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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-- SRAM
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SRAM_nWE : OUT STD_LOGIC;
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SRAM_CE : OUT STD_LOGIC;
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SRAM_nOE : OUT STD_LOGIC;
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SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END MINI_LFR_top;
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ARCHITECTURE beh OF MINI_LFR_top IS
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SIGNAL clk_50_s : STD_LOGIC := '0';
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SIGNAL clk_25 : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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--
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SIGNAL errorn : STD_LOGIC;
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-- UART AHB ---------------------------------------------------------------
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SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
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SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
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-- UART APB ---------------------------------------------------------------
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SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
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SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
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--
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SIGNAL I00_s : STD_LOGIC;
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--
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CONSTANT NB_APB_SLAVE : INTEGER := 1;
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CONSTANT NB_AHB_SLAVE : INTEGER := 1;
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CONSTANT NB_AHB_MASTER : INTEGER := 1;
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SIGNAL apbi_ext : apb_slv_in_type;
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SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);
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SIGNAL ahbi_s_ext : ahb_slv_in_type;
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SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);
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SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
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SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
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SIGNAL SRAM_CE_V : STD_LOGIC_VECTOR(1 downto 0);
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BEGIN -- beh
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-----------------------------------------------------------------------------
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-- CLK
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-----------------------------------------------------------------------------
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PROCESS(clk_50)
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BEGIN
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IF clk_50'EVENT AND clk_50 = '1' THEN
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clk_50_s <= NOT clk_50_s;
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END IF;
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END PROCESS;
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PROCESS(clk_50_s)
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BEGIN
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IF clk_50_s'EVENT AND clk_50_s = '1' THEN
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clk_25 <= NOT clk_25;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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PROCESS (clk_25, reset)
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BEGIN -- PROCESS
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IF reset = '0' THEN -- asynchronous reset (active low)
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LED0 <= '0';
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LED1 <= '0';
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LED2 <= '0';
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IO1 <= '0';
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IO2 <= '1';
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IO3 <= '0';
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IO4 <= '0';
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IO5 <= '0';
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IO6 <= '0';
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IO7 <= '0';
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IO8 <= '0';
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IO9 <= '0';
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IO10 <= '0';
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IO11 <= '0';
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ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
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LED0 <= '0';
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LED1 <= '1';
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LED2 <= BP0;
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IO1 <= '1';
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IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
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IO3 <= ADC_SDO(0);
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IO4 <= ADC_SDO(1);
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IO5 <= ADC_SDO(2);
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IO6 <= ADC_SDO(3);
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IO7 <= ADC_SDO(4);
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IO8 <= ADC_SDO(5);
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IO9 <= ADC_SDO(6);
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IO10 <= ADC_SDO(7);
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IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
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END IF;
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END PROCESS;
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PROCESS (clk_49, reset)
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BEGIN -- PROCESS
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IF reset = '0' THEN -- asynchronous reset (active low)
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I00_s <= '0';
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ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
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I00_s <= NOT I00_s;
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END IF;
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END PROCESS;
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IO0 <= I00_s;
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--UARTs
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nCTS1 <= '1';
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nCTS2 <= '1';
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nDCD2 <= '1';
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--EXT CONNECTOR
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--SPACE WIRE
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SPW_EN <= '0'; -- 0 => off
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SPW_NOM_DOUT <= '0';
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SPW_NOM_SOUT <= '0';
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SPW_RED_DOUT <= '0';
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SPW_RED_SOUT <= '0';
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ADC_nCS <= '0';
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ADC_CLK <= '0';
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leon3_soc_1: leon3_soc
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GENERIC MAP (
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fabtech => apa3e,
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memtech => apa3e,
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padtech => inferred,
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clktech => inferred,
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disas => 0,
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dbguart => 0,
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pclow => 2,
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clk_freq => 25000,
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NB_CPU => 1,
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ENABLE_FPU => 0,
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FPU_NETLIST => 0,
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ENABLE_DSU => 1,
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ENABLE_AHB_UART => 1,
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ENABLE_APB_UART => 1,
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ENABLE_IRQMP => 1,
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ENABLE_GPT => 1,
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NB_AHB_MASTER => NB_AHB_MASTER,
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NB_AHB_SLAVE => NB_AHB_SLAVE,
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NB_APB_SLAVE => NB_APB_SLAVE)
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PORT MAP (
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clk => clk_25,
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reset => reset,
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errorn => errorn,
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ahbrxd => TXD1,
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ahbtxd => RXD1,
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urxd1 => TXD2,
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utxd1 => RXD2,
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address => SRAM_A,
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data => SRAM_DQ,
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nSRAM_BE0 => SRAM_nBE(0),
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nSRAM_BE1 => SRAM_nBE(1),
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nSRAM_BE2 => SRAM_nBE(2),
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nSRAM_BE3 => SRAM_nBE(3),
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nSRAM_WE => SRAM_nWE,
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nSRAM_CE => SRAM_CE_V,
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nSRAM_OE => SRAM_nOE,
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nSRAM_READY=> open,
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apbi_ext => apbi_ext,
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apbo_ext => apbo_ext,
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ahbi_s_ext => ahbi_s_ext,
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ahbo_s_ext => ahbo_s_ext,
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ahbi_m_ext => ahbi_m_ext,
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ahbo_m_ext => ahbo_m_ext);
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SRAM_CE <= SRAM_CE_V(0);
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END beh;
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