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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_lfr_filter_coeff.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.data_type_pkg.ALL;
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USE lpp.chirp_pkg.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.general_purpose.ALL;
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ENTITY testbench IS
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END;
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ARCHITECTURE behav OF testbench IS
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COMPONENT IIR_CEL_TEST
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PORT (
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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sample_in_val : IN STD_LOGIC;
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sample_in : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
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sample_out_val : OUT STD_LOGIC;
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sample_out : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0));
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END COMPONENT;
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COMPONENT IIR_CEL_TEST_v3
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PORT (
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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sample_in1_val : IN STD_LOGIC;
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sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
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sample_in2_val : IN STD_LOGIC;
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sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
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sample_out1_val : OUT STD_LOGIC;
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sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0);
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sample_out2_val : OUT STD_LOGIC;
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sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0));
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END COMPONENT;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL clk_24k : STD_LOGIC := '0';
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SIGNAL clk_24k_r : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC;
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SIGNAL sample : Samples(7 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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SIGNAL sample_val_2 : STD_LOGIC;
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SIGNAL data_chirp : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL data_chirp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL sample_s : samplT(7 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_out_s : samplT(7 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_out_s2 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_out_val : STD_LOGIC;
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SIGNAL sample_out1_val : STD_LOGIC;
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SIGNAL sample_out2_val : STD_LOGIC;
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SIGNAL sample_out1 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_out2 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_out1_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_out2_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_s_v3 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
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SIGNAL sample_val_v3 : STD_LOGIC;
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SIGNAL sample_val_v3_2 : STD_LOGIC;
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SIGNAL temp : STD_LOGIC;
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BEGIN
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-----------------------------------------------------------------------------
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-- CLOCK and RESET
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-----------------------------------------------------------------------------
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clk <= NOT clk AFTER 5 ns;
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk = '1';
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rstn <= '0';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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WAIT FOR 30 ms;
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REPORT "*** END simulation ***" SEVERITY failure;
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WAIT;
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END PROCESS;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- LPP_LFR_FILTER
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-----------------------------------------------------------------------------
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lpp_lfr_filter_1: lpp_lfr_filter
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GENERIC MAP (
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Mem_use => use_CEL)
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PORT MAP (
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sample => sample,
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sample_val => sample_val,
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clk => clk,
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rstn => rstn,
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data_shaping_SP0 => '0',
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data_shaping_SP1 => '0',
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data_shaping_R0 => '0',
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data_shaping_R1 => '0',
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data_shaping_R2 => '0',
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sample_f0_val => OPEN,
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sample_f1_val => OPEN,
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sample_f2_val => OPEN,
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sample_f3_val => OPEN,
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sample_f0_wdata => OPEN,
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sample_f1_wdata => OPEN,
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sample_f2_wdata => OPEN,
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sample_f3_wdata => OPEN);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- SAMPLE GENERATION
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-----------------------------------------------------------------------------
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clk_24k <= NOT clk_24k AFTER 20345 ns;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_val <= '0';
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sample_val_2 <= '0';
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clk_24k_r <= '0';
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temp <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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clk_24k_r <= clk_24k;
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IF clk_24k = '1' AND clk_24k_r = '0' THEN
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sample_val <= '1';
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sample_val_2 <= temp;
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temp <= NOT temp;
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ELSE
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sample_val <= '0';
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sample_val_2 <= '0';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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chirp_1: chirp
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GENERIC MAP (
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LOW_FREQUENCY_LIMIT => 0,
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HIGH_FREQUENCY_LIMIT => 2000,
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NB_POINT_TO_GEN => 10000,
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AMPLITUDE => 100,
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NB_BITS => 16)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => '1',
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data_ack => sample_val,
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data => data_chirp);
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chirp_2: chirp
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GENERIC MAP (
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LOW_FREQUENCY_LIMIT => 0,
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HIGH_FREQUENCY_LIMIT => 2000,
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NB_POINT_TO_GEN => 100000,
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AMPLITUDE => 200,
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NB_BITS => 16)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => '1',
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data_ack => sample_val,
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data => data_chirp_2);
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all_channel: FOR I IN 0 TO 3 GENERATE
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sample(2*I) <= data_chirp;
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sample(2*I+1) <= data_chirp_2;
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END GENERATE all_channel;
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-----------------------------------------------------------------------------
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all_channel_test: FOR I IN 0 TO 3 GENERATE
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all_bit_test: FOR J IN 0 TO 15 GENERATE
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sample_s(2*I ,J) <= data_chirp(J);
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sample_s(2*I+1,J) <= data_chirp_2(J);
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END GENERATE all_bit_test;
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sample_s(2*I,16) <= data_chirp(15);
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sample_s(2*I,17) <= data_chirp(15);
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sample_s(2*I+1,16) <= data_chirp_2(15);
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sample_s(2*I+1,17) <= data_chirp_2(15);
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END GENERATE all_channel_test;
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IIR_CEL_TEST_1: IIR_CEL_TEST
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PORT MAP (
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rstn => rstn,
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clk => clk,
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sample_in_val => sample_val,
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sample_in => sample_s,
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sample_out_val => sample_out_val,
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sample_out => sample_out_s);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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all_channel: FOR I IN 0 TO 7 LOOP
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all_bit: FOR J IN 0 TO 17 LOOP
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sample_out_s2(I,J) <= '0';
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END LOOP all_bit;
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END LOOP all_channel;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF sample_out_val = '1' THEN
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sample_out_s2 <= sample_out_s;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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IIR_CEL_TEST_v3_1: IIR_CEL_TEST_v3
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PORT MAP (
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rstn => rstn,
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clk => clk,
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sample_in1_val => sample_val_v3,
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sample_in1 => sample_s_v3,
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sample_in2_val => sample_val_v3_2,
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sample_in2 => sample_s_v3,
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sample_out1_val => sample_out1_val,
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sample_out1 => sample_out1,
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sample_out2_val => sample_out2_val,
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sample_out2 => sample_out2);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF sample_val = '1' THEN
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sample_s_v3 <= sample_s;
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END IF;
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sample_val_v3 <= sample_val;
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sample_val_v3_2 <= sample_val_2;
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IF sample_out1_val = '1' THEN
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sample_out1_reg <= sample_out1;
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END IF;
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IF sample_out2_val = '1' THEN
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sample_out2_reg <= sample_out2;
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END IF;
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END IF;
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END PROCESS;
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END;
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