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Update MINI LFR constraint's files
Update MINI LFR constraint's files
Alexis Jeandet - - Load All Authors

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top.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by GRLIB script generator -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
</header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
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<file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Word_Cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<library xil_pn:name="lpp"/>
</file>
<file xil_pn:name="../../lib/cypress/ssram/components.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="cypress"/>
</file>
<file xil_pn:name="../../lib/cypress/ssram/package_utility.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="cypress"/>
</file>
<file xil_pn:name="../../lib/cypress/ssram/cy7c1354b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="cypress"/>
</file>
<file xil_pn:name="../../lib/cypress/ssram/cy7c1380d.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="cypress"/>
</file>
<file xil_pn:name="../../lib/work/debug/debug.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="work"/>
</file>
<file xil_pn:name="../../lib/work/debug/grtestmod.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="work"/>
</file>
<file xil_pn:name="../../lib/work/debug/cpu_disas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<library xil_pn:name="work"/>
</file>
<file xil_pn:name="config.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ahbrom.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="leon3mp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="testbench.vhd" xil_pn:type="FILE_VHDL">
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</file>
</files>
<properties>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="true"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="()"/>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Create Mask File" xil_pn:value="true"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="true"/>
<property xil_pn:name="Device" xil_pn:value="A3PE1500"/>
<property xil_pn:name="Device Family" xil_pn:value="PROASIC3"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="true"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="None"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|rtl"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top"/>
<property xil_pn:name="Macro Search Path" xil_pn:value="../../netlists/xilinx/PROASIC3"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value=""/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value=""/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="high"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="top"/>
<property xil_pn:name="PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2" xil_pn:value="true"/>
<property xil_pn:name="PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2" xil_pn:value="true"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs"/>
<property xil_pn:name="Package" xil_pn:value=""""/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed"/>
<property xil_pn:name="Speed Grade" xil_pn:value="Std"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
</properties>
<bindings/>
<libraries>
<library xil_pn:name="grlib"/>
<library xil_pn:name="proasic3"/>
<library xil_pn:name="dware"/>
<library xil_pn:name="synplify"/>
<library xil_pn:name="techmap"/>
<library xil_pn:name="opencores"/>
<library xil_pn:name="gaisler"/>
<library xil_pn:name="lpp"/>
<library xil_pn:name="cypress"/>
<library xil_pn:name="work"/>
</libraries>
<partitions>
<partition xil_pn:name="/top"/>
</partitions>
</project>