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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.general_purpose.all;
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--IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100
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--NOT =0101 AND =0110 OR =0111 XOR =1000
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--SHIFTleft =1001 SHIFTright =1010
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entity ALU is
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generic(
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Arith_en : integer := 1;
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Logic_en : integer := 1;
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Input_SZ_1 : integer := 16;
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Input_SZ_2 : integer := 9
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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ctrl : in std_logic_vector(3 downto 0);
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OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
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OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
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RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
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);
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end entity;
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architecture ar_ALU of ALU is
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signal clr_MAC : std_logic:='1';
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begin
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clr_MAC <= '1' when ctrl = "0100" else '0';
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arith : if Arith_en = 1 generate
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MACinst : MAC
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generic map(
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Input_SZ_A => Input_SZ_1,
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Input_SZ_B => Input_SZ_2
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)
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port map(
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clk => clk,
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reset => reset,
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clr_MAC => clr_MAC,
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MAC_MUL_ADD => ctrl(1 downto 0),
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OP1 => OP1,
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OP2 => OP2,
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RES => RES
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);
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end generate;
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process(clk,reset)
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begin
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if reset = '0' then
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elsif clk'event and clk ='1' then
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end if;
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end process;
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end architecture;
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