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-----------------------------------------------------------------------------
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-- --
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-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
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-- --
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-- This source file may be used and distributed without restriction --
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-- provided that this copyright statement is not removed from the file --
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-- and that any derivative work contains this copyright notice. --
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-- --
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-- Primitive library for post synthesis simulation --
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-- These models are not intended for efficient synthesis --
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-- --
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-----------------------------------------------------------------------------
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--pragma translate_off
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library ieee;
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use ieee.std_logic_1164.all;
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entity prim_counter is
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generic (w : integer := 8);
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port (
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q : buffer std_logic_vector(w - 1 downto 0);
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cout : out std_logic;
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d : in std_logic_vector(w - 1 downto 0);
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cin : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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load : in std_logic;
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en : in std_logic;
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updn : in std_logic
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);
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end prim_counter;
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architecture beh of prim_counter is
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signal nextq : std_logic_vector(w - 1 downto 0);
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begin
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nxt: process (q, cin, updn)
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variable i : integer;
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variable nextc, c : std_logic;
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begin
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nextc := cin;
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for i in 0 to w - 1 loop
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c := nextc;
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nextq(i) <= c xor (not updn) xor q(i);
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nextc := (c and (not updn)) or
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(c and q(i)) or
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((not updn) and q(i));
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end loop;
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cout <= nextc;
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end process;
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ff : process (clk, rst)
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begin
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if rst = '1' then
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q <= (others => '0');
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elsif rising_edge(clk) then
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q <= nextq;
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end if;
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end process ff;
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end beh;
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library ieee;
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use ieee.std_logic_1164.all;
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entity prim_dff is
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port (q : out std_logic;
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d : in std_logic;
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clk : in std_logic;
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r : in std_logic := '0';
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s : in std_logic := '0');
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end prim_dff;
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architecture beh of prim_dff is
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begin
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ff : process (clk, r, s)
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begin
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if r = '1' then
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q <= '0';
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elsif s = '1' then
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q <= '1';
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elsif rising_edge(clk) then
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q <= d;
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end if;
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end process ff;
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end beh;
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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.std_logic_1164.all;
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entity prim_sdff is
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port (q : out std_logic;
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d : in std_logic;
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c : in std_logic;
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r : in std_logic := '0';
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s : in std_logic := '0');
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end prim_sdff;
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architecture beh of prim_sdff is
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begin
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ff : process(c)
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begin
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if rising_edge(c) then
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if r = '1' then
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q <= '0';
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elsif s = '1' then
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q <= '1';
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else
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q <= d;
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end if;
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end if;
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end process ff;
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end beh;
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library ieee;
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use ieee.std_logic_1164.all;
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entity prim_latch is
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port (q : out std_logic;
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d : in std_logic;
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clk : in std_logic;
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r : in std_logic := '0';
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s : in std_logic := '0');
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end prim_latch;
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architecture beh of prim_latch is
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begin
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q <= '0' when r = '1' else
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'1' when s = '1' else
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d when clk = '1';
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end beh;
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----------------------------------------------------------------------------
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-- Zero ohm resistors: Hardi's solution to connect two inout ports.
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----------------------------------------------------------------------------
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-- Copyright (c) 1995, Ben Cohen. All rights reserved.
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-- This model can be used in conjunction with the Kluwer Academic book
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-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
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-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
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-- which discusses guidelines and testbench design issues.
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--
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-- This source file for the ZERO Ohm resistor model may be used and
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-- distributed without restriction provided that this copyright
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-- statement is not removed from the file and that any derivative work
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-- contains this copyright notice.
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-- File name : Zohm_ea.vhd
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-- Description: This package, entity, and architecture provide
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-- the definition of a zero ohm component (A, B).
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--
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-- The applications of this component include:
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-- . Normal operation of a jumper wire (data flowing in both directions)
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--
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-- The component consists of 2 ports:
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-- . Port A: One side of the pass-through switch
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-- . Port B: The other side of the pass-through switch
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-- The model is sensitive to transactions on all ports. Once a
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-- transaction is detected, all other transactions are ignored
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-- for that simulation time (i.e. further transactions in that
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-- delta time are ignored).
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--
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-- The width of the pass-through switch is defined through the
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-- generic "width_g". The pass-through control and operation
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-- is defined on a per bit basis (i.e. one process per bit).
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--
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-- Model Limitations and Restrictions:
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-- Signals asserted on the ports of the error injector should not have
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-- transactions occuring in multiple delta times because the model
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-- is sensitive to transactions on port A, B ONLY ONCE during
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-- a simulation time. Thus, once fired, a process will
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-- not refire if there are multiple transactions occuring in delta times.
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-- This condition may occur in gate level simulations with
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-- ZERO delays because transactions may occur in multiple delta times.
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--
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--
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-- Acknowledgement: The author thanks Steve Schoessow and Johan Sandstrom
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-- for their contributions and discussions in the enhancement and
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-- verification of this model.
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--
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--=================================================================
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-- Revisions:
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-- Date Author Revision Comment
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-- 07-13-95 Ben Cohen Rev A Creation
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-- VhdlCohen@aol.com
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-------------------------------------------------------------
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library IEEE;
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use IEEE.Std_Logic_1164.all;
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entity ZeroOhm1 is
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port
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(A : inout Std_Logic;
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B : inout Std_Logic
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);
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end ZeroOhm1;
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architecture ZeroOhm1_a of ZeroOhm1 is
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-- attribute syn_black_box : boolean;
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-- attribute syn_feedthrough : boolean;
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-- attribute syn_black_box of all : architecture is true;
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-- attribute syn_feedthrough of all : architecture is true;
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begin
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ABC0_Lbl: process
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variable ThenTime_v : time;
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begin
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wait on A'transaction, B'transaction
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until ThenTime_v /= now;
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-- Break
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ThenTime_v := now;
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A <= 'Z';
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B <= 'Z';
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wait for 0 ns;
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-- Make
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A <= B;
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B <= A;
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end process ABC0_Lbl;
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end ZeroOhm1_a;
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-------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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entity prim_ramd is
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generic (
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data_width : integer := 4;
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addr_width : integer := 5);
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port (
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dout : out std_logic_vector(data_width-1 downto 0);
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aout : in std_logic_vector(addr_width-1 downto 0);
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din : in std_logic_vector(data_width-1 downto 0);
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ain : in std_logic_vector(addr_width-1 downto 0);
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we : in std_logic;
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clk : in std_logic);
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end prim_ramd;
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architecture beh of prim_ramd is
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constant depth : integer := 2** addr_width;
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type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
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signal mem: mem_type;
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begin
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dout <= mem(conv_integer(aout));
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process (clk)
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begin
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if rising_edge(clk) then
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if (we = '1') then
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mem(conv_integer(ain)) <= din;
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end if;
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end if;
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end process;
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end beh ;
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library ieee;
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use ieee.std_logic_1164.all;
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package components is
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component prim_counter
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generic (w : integer);
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port (
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q : buffer std_logic_vector(w - 1 downto 0);
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cout : out std_logic;
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d : in std_logic_vector(w - 1 downto 0);
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cin : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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load : in std_logic;
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en : in std_logic;
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updn : in std_logic
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);
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end component;
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component prim_dff
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port (q : out std_logic;
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d : in std_logic;
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clk : in std_logic;
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r : in std_logic := '0';
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s : in std_logic := '0');
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end component;
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component prim_sdff
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port(q : out std_logic;
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d : in std_logic;
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c : in std_logic;
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r : in std_logic := '0';
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s : in std_logic := '0');
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end component;
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component prim_latch
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port (q : out std_logic;
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d : in std_logic;
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clk : in std_logic;
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r : in std_logic := '0';
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s : in std_logic := '0');
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end component;
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component prim_ramd is
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generic (
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data_width : integer := 4;
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addr_width : integer := 5);
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port (
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dout : out std_logic_vector(data_width-1 downto 0);
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aout : in std_logic_vector(addr_width-1 downto 0);
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din : in std_logic_vector(data_width-1 downto 0);
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ain : in std_logic_vector(addr_width-1 downto 0);
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we : in std_logic;
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clk : in std_logic);
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end component;
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end components;
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-- pragma translate_on
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