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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: memctrl
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-- File: memctrl.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Memory controller package
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.log2;
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library techmap;
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use techmap.gencomp.all;
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package memctrl is
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type memory_in_type is record
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data : std_logic_vector(31 downto 0); -- Data bus address
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brdyn : std_logic;
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bexcn : std_logic;
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writen : std_logic;
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wrn : std_logic_vector(3 downto 0);
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bwidth : std_logic_vector(1 downto 0);
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sd : std_logic_vector(63 downto 0);
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cb : std_logic_vector(15 downto 0);
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scb : std_logic_vector(15 downto 0);
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edac : std_logic;
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end record;
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constant memory_in_none : memory_in_type :=
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((others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
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(others => '0'), (others => '0'), (others => '0'), '0');
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type memory_out_type is record
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address : std_logic_vector(31 downto 0);
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data : std_logic_vector(31 downto 0);
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sddata : std_logic_vector(63 downto 0);
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ramsn : std_logic_vector(7 downto 0);
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ramoen : std_logic_vector(7 downto 0);
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ramn : std_ulogic;
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romn : std_ulogic;
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mben : std_logic_vector(3 downto 0);
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iosn : std_logic;
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romsn : std_logic_vector(7 downto 0);
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oen : std_logic;
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writen : std_logic;
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wrn : std_logic_vector(3 downto 0);
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bdrive : std_logic_vector(3 downto 0);
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vbdrive : std_logic_vector(31 downto 0); --vector bus drive
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svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
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read : std_logic;
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sa : std_logic_vector(14 downto 0);
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cb : std_logic_vector(15 downto 0);
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scb : std_logic_vector(15 downto 0);
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vcdrive : std_logic_vector(15 downto 0); --vector bus drive cb
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svcdrive : std_logic_vector(15 downto 0); --vector bus drive cb sdram
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ce : std_ulogic;
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sdram_en : std_ulogic; -- SDRAM enabled
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rs_edac_en : std_ulogic; -- Reed-Solomon enabled
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end record;
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constant memory_out_none : memory_out_type :=
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((others => '0'), (others => '0'), (others => '0'), (others => '1'),
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(others => '1'), '1', '1', (others => '1'), '1', (others => '1'),
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'1', '1', (others => '1'), (others => '1'), (others => '1'),
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(others => '1'), '0', (others => '0'), (others => '1'), (others => '1'),
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(others => '1'), (others => '1'), '0', '0', '0');
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type sdctrl_in_type is record
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wprot : std_ulogic;
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data : std_logic_vector (127 downto 0); -- data in
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cb : std_logic_vector(63 downto 0);
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regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in
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end record;
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constant sdctrl_in_none : sdctrl_in_type :=
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('0', (others => '0'), (others => '0'), (others => '0'));
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type sdctrl_out_type is record
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sdcke : std_logic_vector ( 1 downto 0); -- clk en
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sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
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sdwen : std_ulogic; -- write en
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rasn : std_ulogic; -- row addr stb
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casn : std_ulogic; -- col addr stb
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dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
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bdrive : std_ulogic; -- bus drive
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qdrive : std_ulogic; -- bus drive
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vbdrive : std_logic_vector(63 downto 0); -- vector bus drive
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address : std_logic_vector (16 downto 2); -- address out
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data : std_logic_vector (127 downto 0); -- data out
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cb : std_logic_vector(63 downto 0);
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ce : std_ulogic;
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ba : std_logic_vector (2 downto 0); -- bank address
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sdck : std_logic_vector(2 downto 0);
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moben : std_logic; -- Mobile support
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cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
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cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
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cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase
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cal_rst : std_logic; -- calibration reset
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odt : std_logic_vector(1 downto 0); -- In Die Termination
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conf : std_logic_vector(63 downto 0);
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oct : std_logic; -- On Chip Termination
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vcbdrive : std_logic_vector(31 downto 0); -- cb vector bus drive
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cbdqm : std_logic_vector(7 downto 0);
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cbcal_en : std_logic_vector(3 downto 0);
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cbcal_inc : std_logic_vector(3 downto 0);
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read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
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-- cycles (not including phy delays)
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-- PHY-specific register interface
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regwdata : std_logic_vector(63 downto 0);
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regwrite : std_logic_vector(1 downto 0);
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end record;
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constant sdctrl_out_none : sdctrl_out_type :=
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((others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
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'0', '0', (others => '0'), (others => '0'), (others => '0'),
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(others => '0'), '0', (others => '0'), (others => '0'), '0',
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(others => '0'), (others => '0'), (others => '0'), '0',
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(others => '0'), (others => '0'), '0', (others => '0'),
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(others => '0'), (others => '0'), (others => '0'), "00000000",
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(others => '0'), "00");
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type sdram_out_type is record
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sdcke : std_logic_vector ( 1 downto 0); -- clk en
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sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
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sdwen : std_ulogic; -- write en
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rasn : std_ulogic; -- row addr stb
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casn : std_ulogic; -- col addr stb
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dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
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end record;
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component sdctrl
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#f00#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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wprot : integer := 0;
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invclk : integer := 0;
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fast : integer := 0;
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pwron : integer := 0;
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sdbits : integer := 32;
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oepol : integer := 0;
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pageburst : integer := 0;
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mobile : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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sdi : in sdctrl_in_type;
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sdo : out sdctrl_out_type
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);
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end component;
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component sdctrl64
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#f00#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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wprot : integer := 0;
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invclk : integer := 0;
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fast : integer := 0;
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pwron : integer := 0;
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oepol : integer := 0;
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pageburst : integer := 0;
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mobile : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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sdi : in sdctrl_in_type;
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sdo : out sdctrl_out_type
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);
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end component;
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component ftsdctrl is
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#f00#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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wprot : integer := 0;
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invclk : integer := 0;
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fast : integer := 0;
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pwron : integer := 0;
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sdbits : integer := 32;
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edacen : integer := 1;
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errcnt : integer := 0;
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cntbits : integer range 1 to 8 := 1;
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oepol : integer := 0;
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pageburst : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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sdi : in sdctrl_in_type;
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sdo : out sdctrl_out_type
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);
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end component;
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component ftsdctrl64
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#f00#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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wprot : integer := 0;
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invclk : integer := 0;
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fast : integer := 0;
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pwron : integer := 0;
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oepol : integer := 0;
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pageburst : integer := 0;
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mobile : integer := 0;
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edac : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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sdi : in sdctrl_in_type;
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sdo : out sdctrl_out_type
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);
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end component;
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component srctrl
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generic (
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hindex : integer := 0;
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romaddr : integer := 0;
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rommask : integer := 16#ff0#;
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ramaddr : integer := 16#400#;
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rammask : integer := 16#ff0#;
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ioaddr : integer := 16#200#;
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iomask : integer := 16#ff0#;
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ramws : integer := 0;
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romws : integer := 2;
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iows : integer := 2;
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rmw : integer := 0;
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prom8en : integer := 0;
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oepol : integer := 0;
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srbanks : integer range 1 to 5 := 1;
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banksz : integer range 0 to 13 := 13;
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romasel : integer range 0 to 28 := 19
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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sri : in memory_in_type;
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sro : out memory_out_type;
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sdo : out sdctrl_out_type
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);
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end component;
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component ftsrctrl is
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generic (
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hindex : integer := 0;
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romaddr : integer := 0;
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rommask : integer := 16#ff0#;
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ramaddr : integer := 16#400#;
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rammask : integer := 16#ff0#;
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ioaddr : integer := 16#200#;
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iomask : integer := 16#ff0#;
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ramws : integer := 0;
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romws : integer := 2;
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iows : integer := 2;
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rmw : integer := 0;
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srbanks : integer range 1 to 8 := 1;
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banksz : integer range 0 to 15 := 15;
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rombanks : integer range 1 to 8 := 1;
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rombanksz : integer range 0 to 15 := 15;
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rombankszdef : integer range 0 to 15 := 15;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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edacen : integer range 0 to 1 := 1;
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errcnt : integer range 0 to 1 := 0;
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cntbits : integer range 1 to 8 := 1;
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wsreg : integer := 0;
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oepol : integer := 0;
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prom8en : integer := 0;
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netlist : integer := 0;
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tech : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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sri : in memory_in_type;
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sro : out memory_out_type;
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sdo : out sdctrl_out_type
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);
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end component;
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type sdram_in_type is record
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haddr : std_logic_vector(31 downto 0); -- memory address
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rhaddr : std_logic_vector(31 downto 0); -- latched memory address
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hready : std_ulogic;
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hsize : std_logic_vector(1 downto 0);
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hsel : std_ulogic;
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hwrite : std_ulogic;
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htrans : std_logic_vector(1 downto 0);
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rhtrans : std_logic_vector(1 downto 0);
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nhtrans : std_logic_vector(1 downto 0);
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idle : std_ulogic;
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enable : std_ulogic;
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error : std_ulogic;
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merror : std_ulogic;
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brmw : std_ulogic;
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edac : std_ulogic;
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srdis : std_logic;
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end record;
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|
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type sdram_mctrl_out_type is record
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|
address : std_logic_vector(16 downto 2);
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busy : std_ulogic;
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aload : std_ulogic;
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bdrive : std_ulogic;
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|
hready : std_ulogic;
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hsel : std_ulogic;
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bsel : std_ulogic;
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|
hresp : std_logic_vector (1 downto 0);
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vhready : std_ulogic;
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prdata : std_logic_vector (31 downto 0);
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|
end record;
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|
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|
|
|
type wprot_out_type is record
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|
|
wprothit : std_ulogic;
|
|
|
end record;
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|
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|
|
|
component sdmctrl
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|
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generic (
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|
|
pindex : integer := 0;
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|
invclk : integer := 0;
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|
fast : integer := 0;
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|
wprot : integer := 0;
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|
|
sdbits : integer := 32;
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|
pageburst : integer := 0;
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|
mobile : integer := 0
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|
|
);
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|
|
port (
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|
rst : in std_ulogic;
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|
|
clk : in std_ulogic;
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|
|
sdi : in sdram_in_type;
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|
|
sdo : out sdram_out_type;
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|
|
apbi : in apb_slv_in_type;
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|
|
wpo : in wprot_out_type;
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|
|
sdmo : out sdram_mctrl_out_type
|
|
|
);
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|
|
end component;
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|
|
|
|
|
component ftsdmctrl
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|
|
generic (
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|
|
pindex : integer := 0;
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|
invclk : integer := 0;
|
|
|
fast : integer := 0;
|
|
|
wprot : integer := 0;
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|
|
sdbits : integer := 32;
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|
|
syncrst : integer := 0;
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|
pageburst : integer := 0
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|
|
);
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|
|
port (
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|
|
rst : in std_ulogic;
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|
|
clk : in std_ulogic;
|
|
|
sdi : in sdram_in_type;
|
|
|
sdo : out sdram_out_type;
|
|
|
apbi : in apb_slv_in_type;
|
|
|
wpo : in wprot_out_type;
|
|
|
sdmo : out sdram_mctrl_out_type
|
|
|
);
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|
|
end component;
|
|
|
|
|
|
component ftmctrl
|
|
|
generic (
|
|
|
hindex : integer := 0;
|
|
|
pindex : integer := 0;
|
|
|
romaddr : integer := 16#000#;
|
|
|
rommask : integer := 16#E00#;
|
|
|
ioaddr : integer := 16#200#;
|
|
|
iomask : integer := 16#E00#;
|
|
|
ramaddr : integer := 16#400#;
|
|
|
rammask : integer := 16#C00#;
|
|
|
paddr : integer := 0;
|
|
|
pmask : integer := 16#fff#;
|
|
|
wprot : integer := 0;
|
|
|
invclk : integer := 0;
|
|
|
fast : integer := 0;
|
|
|
romasel : integer := 28;
|
|
|
sdrasel : integer := 29;
|
|
|
srbanks : integer := 4;
|
|
|
ram8 : integer := 0;
|
|
|
ram16 : integer := 0;
|
|
|
sden : integer := 0;
|
|
|
sepbus : integer := 0;
|
|
|
sdbits : integer := 32;
|
|
|
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
|
|
|
oepol : integer := 0;
|
|
|
edac : integer := 0;
|
|
|
syncrst : integer := 0;
|
|
|
pageburst : integer := 0;
|
|
|
scantest : integer := 0;
|
|
|
writefb : integer := 0;
|
|
|
netlist : integer := 0;
|
|
|
tech : integer := 0
|
|
|
);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
memi : in memory_in_type;
|
|
|
memo : out memory_out_type;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
apbi : in apb_slv_in_type;
|
|
|
apbo : out apb_slv_out_type;
|
|
|
wpo : in wprot_out_type;
|
|
|
sdo : out sdram_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ssrctrl
|
|
|
generic (
|
|
|
hindex : integer := 0;
|
|
|
pindex : integer := 0;
|
|
|
romaddr : integer := 0;
|
|
|
rommask : integer := 16#ff0#;
|
|
|
ramaddr : integer := 16#400#;
|
|
|
rammask : integer := 16#ff0#;
|
|
|
ioaddr : integer := 16#200#;
|
|
|
iomask : integer := 16#ff0#;
|
|
|
paddr : integer := 0;
|
|
|
pmask : integer := 16#fff#;
|
|
|
oepol : integer := 0;
|
|
|
bus16 : integer := 0
|
|
|
);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
apbi : in apb_slv_in_type;
|
|
|
apbo : out apb_slv_out_type;
|
|
|
sri : in memory_in_type;
|
|
|
sro : out memory_out_type
|
|
|
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
type ddrmem_in_type is record
|
|
|
cke : std_ulogic;
|
|
|
cs : std_logic_vector(1 downto 0);
|
|
|
control : std_logic_vector(2 downto 0); --RAS,CAS,WE
|
|
|
ba : std_logic_vector(1 downto 0);
|
|
|
adr : std_logic_vector(13 downto 0);
|
|
|
dq : std_logic_vector(63 downto 0);
|
|
|
dm : std_logic_vector(15 downto 0);
|
|
|
dqs : std_logic_vector(15 downto 0);
|
|
|
dq_oe : std_logic_vector(63 downto 0);
|
|
|
dqs_oe : std_logic_vector(15 downto 0);
|
|
|
end record;
|
|
|
|
|
|
type ddrmem_out_type is record
|
|
|
dq : std_logic_vector(63 downto 0);
|
|
|
dqs : std_logic_vector(15 downto 0);
|
|
|
end record;
|
|
|
|
|
|
component ddrctrl
|
|
|
generic (
|
|
|
hindex1 : integer := 0;
|
|
|
haddr1 : integer := 0;
|
|
|
hmask1 : integer := 16#f80#;
|
|
|
hindex2 : integer := 0;
|
|
|
haddr2 : integer := 0;
|
|
|
hmask2 : integer := 16#f80#;
|
|
|
pindex : integer := 3;
|
|
|
paddr : integer := 0;
|
|
|
numahb : integer := 1; -- Allowed: 1, 2
|
|
|
ahb1sepclk : integer := 0; -- Allowed: 0, 1
|
|
|
ahb2sepclk : integer := 0; -- Allowed: 0, 1
|
|
|
modbanks : integer := 1; -- Allowed: 1, 2
|
|
|
numchips : integer := 8; -- Allowed: 1, 2, 4, 8, 16
|
|
|
chipbits : integer := 8; -- Allowed: 4, 8, 16
|
|
|
chipsize : integer := 128; -- Allowed: 64, 128, 256, 512, 1024 (MB)
|
|
|
plldelay : integer := 0; -- Allowed: 0, 1 (Use 200us start up delay)
|
|
|
tech : integer := 0;
|
|
|
clkperiod : integer := 10); -- 100 Mhz
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk0 : in std_ulogic;
|
|
|
clk90 : in std_ulogic;
|
|
|
clk180 : in std_ulogic;
|
|
|
clk270 : in std_ulogic;
|
|
|
hclk1 : in std_ulogic;
|
|
|
hclk2 : in std_ulogic;
|
|
|
pclk : in std_ulogic;
|
|
|
ahb1si : in ahb_slv_in_type;
|
|
|
ahb1so : out ahb_slv_out_type;
|
|
|
ahb2si : in ahb_slv_in_type;
|
|
|
ahb2so : out ahb_slv_out_type;
|
|
|
apbsi : in apb_slv_in_type;
|
|
|
apbso : out apb_slv_out_type;
|
|
|
-- dapbso : out apb_slv_out_type;
|
|
|
ddsi : out ddrmem_in_type;
|
|
|
ddso : in ddrmem_out_type);
|
|
|
end component;
|
|
|
|
|
|
component ftsrctrl_v1
|
|
|
generic (
|
|
|
hindex: Integer := 1;
|
|
|
romaddr: Integer := 16#000#;
|
|
|
rommask: Integer := 16#ff0#;
|
|
|
ramaddr: Integer := 16#400#;
|
|
|
rammask: Integer := 16#ff0#;
|
|
|
ioaddr: Integer := 16#200#;
|
|
|
iomask: Integer := 16#ff0#;
|
|
|
ramws: Integer := 0;
|
|
|
romws: Integer := 0;
|
|
|
iows: Integer := 0;
|
|
|
rmw: Integer := 1;
|
|
|
srbanks: Integer range 1 to 8 := 8;
|
|
|
banksz: Integer range 0 to 13 := 0;
|
|
|
rombanks: Integer range 1 to 8 := 8;
|
|
|
rombanksz: Integer range 0 to 13 := 0;
|
|
|
rombankszdef: Integer range 0 to 13 := 6;
|
|
|
romasel: Integer range 0 to 28 := 0;
|
|
|
pindex: Integer := 0;
|
|
|
paddr: Integer := 16#000#;
|
|
|
pmask: Integer := 16#fff#;
|
|
|
edacen: Integer range 0 to 1 := 1;
|
|
|
errcnt: Integer range 0 to 1 := 0;
|
|
|
cntbits: Integer range 1 to 8 := 1;
|
|
|
wsreg: Integer := 1;
|
|
|
oepol: Integer := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
apbi : in apb_slv_in_type;
|
|
|
apbo : out apb_slv_out_type;
|
|
|
sri : in memory_in_type;
|
|
|
sro : out memory_out_type;
|
|
|
sdo : out sdctrl_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddrsp
|
|
|
generic (
|
|
|
hindex : integer := 0;
|
|
|
haddr : integer := 0;
|
|
|
hmask : integer := 16#f00#;
|
|
|
ioaddr : integer := 16#000#;
|
|
|
iomask : integer := 16#fff#;
|
|
|
MHz : integer := 100;
|
|
|
col : integer := 9;
|
|
|
Mbit : integer := 256;
|
|
|
fast : integer := 0;
|
|
|
pwron : integer := 0;
|
|
|
oepol : integer := 0
|
|
|
);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
sdi : in sdctrl_in_type;
|
|
|
sdo : out sdctrl_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddrsp64a
|
|
|
generic (
|
|
|
memtech : integer := 0;
|
|
|
hindex : integer := 0;
|
|
|
haddr : integer := 0;
|
|
|
hmask : integer := 16#f00#;
|
|
|
ioaddr : integer := 16#000#;
|
|
|
iomask : integer := 16#fff#;
|
|
|
MHz : integer := 100;
|
|
|
col : integer := 9;
|
|
|
Mbyte : integer := 16;
|
|
|
fast : integer := 0;
|
|
|
pwron : integer := 0;
|
|
|
oepol : integer := 0;
|
|
|
mobile : integer := 0;
|
|
|
confapi : integer := 0;
|
|
|
conf0 : integer := 0;
|
|
|
conf1 : integer := 0;
|
|
|
regoutput : integer := 0
|
|
|
);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk_ddr : in std_ulogic;
|
|
|
clk_ahb : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
sdi : in sdctrl_in_type;
|
|
|
sdo : out sdctrl_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddrsp32a
|
|
|
generic (
|
|
|
memtech : integer := 0;
|
|
|
hindex : integer := 0;
|
|
|
haddr : integer := 0;
|
|
|
hmask : integer := 16#f00#;
|
|
|
ioaddr : integer := 16#000#;
|
|
|
iomask : integer := 16#fff#;
|
|
|
MHz : integer := 100;
|
|
|
col : integer := 9;
|
|
|
Mbyte : integer := 16;
|
|
|
fast : integer := 0;
|
|
|
pwron : integer := 0;
|
|
|
oepol : integer := 0;
|
|
|
mobile : integer := 0;
|
|
|
confapi : integer := 0;
|
|
|
conf0 : integer := 0;
|
|
|
conf1 : integer := 0;
|
|
|
regoutput : integer := 0
|
|
|
);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk_ddr : in std_ulogic;
|
|
|
clk_ahb : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
sdi : in sdctrl_in_type;
|
|
|
sdo : out sdctrl_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddrsp16a
|
|
|
generic (
|
|
|
memtech : integer := 0;
|
|
|
hindex : integer := 0;
|
|
|
haddr : integer := 0;
|
|
|
hmask : integer := 16#f00#;
|
|
|
ioaddr : integer := 16#000#;
|
|
|
iomask : integer := 16#fff#;
|
|
|
MHz : integer := 100;
|
|
|
col : integer := 9;
|
|
|
Mbyte : integer := 16;
|
|
|
fast : integer := 0;
|
|
|
pwron : integer := 0;
|
|
|
oepol : integer := 0;
|
|
|
mobile : integer := 0;
|
|
|
confapi : integer := 0;
|
|
|
conf0 : integer := 0;
|
|
|
conf1 : integer := 0;
|
|
|
regoutput : integer := 0
|
|
|
);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk_ddr : in std_ulogic;
|
|
|
clk_ahb : in std_ulogic;
|
|
|
clkread : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
sdi : in sdctrl_in_type;
|
|
|
sdo : out sdctrl_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddrspa
|
|
|
generic (
|
|
|
fabtech : integer := 0;
|
|
|
memtech : integer := 0;
|
|
|
rskew : integer := 0;
|
|
|
hindex : integer := 0;
|
|
|
haddr : integer := 0;
|
|
|
hmask : integer := 16#f00#;
|
|
|
ioaddr : integer := 16#000#;
|
|
|
iomask : integer := 16#fff#;
|
|
|
MHz : integer := 100;
|
|
|
clkmul : integer := 2;
|
|
|
clkdiv : integer := 2;
|
|
|
col : integer := 9;
|
|
|
Mbyte : integer := 16;
|
|
|
rstdel : integer := 200;
|
|
|
pwron : integer := 0;
|
|
|
oepol : integer := 0;
|
|
|
ddrbits : integer := 16;
|
|
|
ahbfreq : integer := 50;
|
|
|
mobile : integer := 0;
|
|
|
confapi : integer := 0;
|
|
|
conf0 : integer := 0;
|
|
|
conf1 : integer := 0;
|
|
|
regoutput : integer range 0 to 1 := 0
|
|
|
);
|
|
|
port (
|
|
|
rst_ddr : in std_ulogic;
|
|
|
rst_ahb : in std_ulogic;
|
|
|
clk_ddr : in std_ulogic;
|
|
|
clk_ahb : in std_ulogic;
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
clkddro : out std_ulogic; -- DCM locked
|
|
|
clkddri : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
|
|
|
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddr2buf is
|
|
|
generic (tech : integer := 0; wabits : integer := 6; wdbits : integer := 8;
|
|
|
rabits : integer := 6; rdbits : integer := 8;
|
|
|
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0);
|
|
|
port (
|
|
|
rclk : in std_ulogic;
|
|
|
renable : in std_ulogic;
|
|
|
raddress : in std_logic_vector((rabits -1) downto 0);
|
|
|
dataout : out std_logic_vector((rdbits -1) downto 0);
|
|
|
wclk : in std_ulogic;
|
|
|
write : in std_ulogic;
|
|
|
writebig : in std_ulogic;
|
|
|
waddress : in std_logic_vector((wabits -1) downto 0);
|
|
|
datain : in std_logic_vector((wdbits -1) downto 0);
|
|
|
testin : in std_logic_vector(3 downto 0) := "0000");
|
|
|
end component;
|
|
|
|
|
|
type ddr_request_type is record
|
|
|
startaddr : std_logic_vector(31 downto 0);
|
|
|
endaddr : std_logic_vector(9 downto 0);
|
|
|
hsize : std_logic_vector(2 downto 0);
|
|
|
hwrite : std_ulogic;
|
|
|
hio : std_ulogic;
|
|
|
maskdata : std_ulogic;
|
|
|
maskcb : std_ulogic;
|
|
|
end record;
|
|
|
|
|
|
component ddr2spax_ahb is
|
|
|
generic (
|
|
|
hindex : integer := 0;
|
|
|
haddr : integer := 0;
|
|
|
hmask : integer := 16#f00#;
|
|
|
ioaddr : integer := 16#000#;
|
|
|
iomask : integer := 16#fff#;
|
|
|
burstlen : integer := 8;
|
|
|
nosync : integer := 0;
|
|
|
ahbbits : integer := ahbdw
|
|
|
);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk_ahb : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
request : out ddr_request_type;
|
|
|
start_tog : out std_logic;
|
|
|
done_tog : in std_logic;
|
|
|
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
|
|
|
wbwdata : out std_logic_vector(ahbdw-1 downto 0);
|
|
|
wbwrite : out std_logic;
|
|
|
wbwritebig: out std_logic;
|
|
|
rbraddr : out std_logic_vector(log2(burstlen*32/ahbdw)-1 downto 0);
|
|
|
rbrdata : in std_logic_vector(ahbdw-1 downto 0)
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ft_ddr2spax_ahb is
|
|
|
generic (
|
|
|
hindex : integer := 0;
|
|
|
haddr : integer := 0;
|
|
|
hmask : integer := 16#f00#;
|
|
|
ioaddr : integer := 16#000#;
|
|
|
iomask : integer := 16#fff#;
|
|
|
burstlen : integer := 8;
|
|
|
nosync : integer := 0;
|
|
|
ahbbits : integer := 64;
|
|
|
bufbits : integer := 96;
|
|
|
ddrbits : integer := 16;
|
|
|
hwidthen : integer := 0
|
|
|
);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk_ahb : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
ce : out std_logic;
|
|
|
request : out ddr_request_type;
|
|
|
start_tog : out std_logic;
|
|
|
done_tog : in std_logic;
|
|
|
wbwaddr : out std_logic_vector(log2(burstlen)-2 downto 0);
|
|
|
wbwdata : out std_logic_vector(bufbits-1 downto 0);
|
|
|
wbwrite : out std_logic;
|
|
|
wbwritebig: out std_logic;
|
|
|
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
|
|
|
rbrdata : in std_logic_vector(bufbits-1 downto 0);
|
|
|
hwidth : in std_logic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddr2spax_ddr is
|
|
|
generic (
|
|
|
ddrbits : integer := 32;
|
|
|
burstlen : integer := 8;
|
|
|
MHz : integer := 100;
|
|
|
TRFC : integer := 130;
|
|
|
col : integer := 9;
|
|
|
Mbyte : integer := 8;
|
|
|
fastahb : integer := 0;
|
|
|
pwron : integer := 0;
|
|
|
oepol : integer := 0;
|
|
|
readdly : integer := 1;
|
|
|
odten : integer := 0;
|
|
|
octen : integer := 0;
|
|
|
dqsgating : integer := 0;
|
|
|
nosync : integer := 0;
|
|
|
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
|
|
|
dqsse : integer range 0 to 1 := 0; -- single ended DQS
|
|
|
ddr_syncrst: integer range 0 to 1 := 0;
|
|
|
chkbits : integer := 0;
|
|
|
bigmem : integer range 0 to 1 := 0;
|
|
|
raspipe : integer range 0 to 1 := 0;
|
|
|
hwidthen : integer range 0 to 1 := 0
|
|
|
);
|
|
|
port (
|
|
|
ddr_rst : in std_ulogic;
|
|
|
clk_ddr : in std_ulogic;
|
|
|
request : in ddr_request_type;
|
|
|
start_tog: in std_logic;
|
|
|
done_tog : out std_logic;
|
|
|
sdi : in sdctrl_in_type;
|
|
|
sdo : out sdctrl_out_type;
|
|
|
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
|
|
|
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
|
|
|
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
|
|
|
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
|
|
|
rbwrite : out std_logic;
|
|
|
hwidth : in std_ulogic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddr2spax is
|
|
|
generic (
|
|
|
memtech : integer := 0;
|
|
|
hindex : integer := 0;
|
|
|
haddr : integer := 0;
|
|
|
hmask : integer := 16#f00#;
|
|
|
ioaddr : integer := 16#000#;
|
|
|
iomask : integer := 16#fff#;
|
|
|
ddrbits : integer := 32;
|
|
|
burstlen : integer := 8;
|
|
|
MHz : integer := 100;
|
|
|
TRFC : integer := 130;
|
|
|
col : integer := 9;
|
|
|
Mbyte : integer := 8;
|
|
|
fastahb : integer := 0;
|
|
|
pwron : integer := 0;
|
|
|
oepol : integer := 0;
|
|
|
readdly : integer := 1;
|
|
|
odten : integer := 0;
|
|
|
octen : integer := 0;
|
|
|
dqsgating : integer := 0;
|
|
|
nosync : integer := 0;
|
|
|
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
|
|
|
dqsse : integer range 0 to 1 := 0; -- single ended DQS
|
|
|
ddr_syncrst: integer range 0 to 1 := 0;
|
|
|
ahbbits : integer := ahbdw;
|
|
|
ft : integer range 0 to 1 := 0;
|
|
|
bigmem : integer range 0 to 1 := 0;
|
|
|
raspipe : integer range 0 to 1 := 0;
|
|
|
hwidthen : integer range 0 to 1 := 0
|
|
|
);
|
|
|
port (
|
|
|
ddr_rst : in std_ulogic;
|
|
|
ahb_rst : in std_ulogic;
|
|
|
clk_ddr : in std_ulogic;
|
|
|
clk_ahb : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
sdi : in sdctrl_in_type;
|
|
|
sdo : out sdctrl_out_type;
|
|
|
hwidth : in std_ulogic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddr2spa
|
|
|
generic (
|
|
|
fabtech : integer := 0;
|
|
|
memtech : integer := 0;
|
|
|
rskew : integer := 0;
|
|
|
hindex : integer := 0;
|
|
|
haddr : integer := 0;
|
|
|
hmask : integer := 16#f00#;
|
|
|
ioaddr : integer := 16#000#;
|
|
|
iomask : integer := 16#fff#;
|
|
|
MHz : integer := 100;
|
|
|
TRFC : integer := 130;
|
|
|
clkmul : integer := 2;
|
|
|
clkdiv : integer := 2;
|
|
|
col : integer := 9;
|
|
|
Mbyte : integer := 16;
|
|
|
rstdel : integer := 200;
|
|
|
pwron : integer := 0;
|
|
|
oepol : integer := 0;
|
|
|
ddrbits : integer := 16;
|
|
|
ahbfreq : integer := 50;
|
|
|
readdly : integer := 1;
|
|
|
ddelayb0 : integer := 0;
|
|
|
ddelayb1 : integer := 0;
|
|
|
ddelayb2 : integer := 0;
|
|
|
ddelayb3 : integer := 0;
|
|
|
ddelayb4 : integer := 0;
|
|
|
ddelayb5 : integer := 0;
|
|
|
ddelayb6 : integer := 0;
|
|
|
ddelayb7 : integer := 0;
|
|
|
cbdelayb0 : integer := 0;
|
|
|
cbdelayb1 : integer := 0;
|
|
|
cbdelayb2 : integer := 0;
|
|
|
cbdelayb3 : integer := 0;
|
|
|
numidelctrl : integer := 4;
|
|
|
norefclk : integer := 0;
|
|
|
odten : integer := 0;
|
|
|
octen : integer := 0;
|
|
|
dqsgating : integer := 0;
|
|
|
nosync : integer := 0;
|
|
|
eightbanks : integer := 0;
|
|
|
dqsse : integer range 0 to 1 := 0;
|
|
|
burstlen : integer range 4 to 128 := 8;
|
|
|
ahbbits : integer := ahbdw;
|
|
|
ft : integer range 0 to 1 := 0;
|
|
|
ftbits : integer := 0;
|
|
|
bigmem : integer range 0 to 1 := 0;
|
|
|
raspipe : integer range 0 to 1 := 0
|
|
|
);
|
|
|
port (
|
|
|
rst_ddr : in std_ulogic;
|
|
|
rst_ahb : in std_ulogic;
|
|
|
clk_ddr : in std_ulogic;
|
|
|
clk_ahb : in std_ulogic;
|
|
|
clkref200 : in std_ulogic;
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
clkddro : out std_ulogic; -- DCM locked
|
|
|
clkddri : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqs
|
|
|
ddr_dqsn : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqsn
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (ddrbits+ftbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
|
|
ce : out std_logic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddrphy_wrap
|
|
|
generic (tech : integer := virtex2; MHz : integer := 100;
|
|
|
rstdelay : integer := 200; dbits : integer := 16;
|
|
|
clk_mul : integer := 2 ; clk_div : integer := 2;
|
|
|
rskew : integer := 0; mobile : integer := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
clkread : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
|
|
|
sdi : out sdctrl_in_type;
|
|
|
sdo : in sdctrl_out_type);
|
|
|
end component;
|
|
|
|
|
|
component ddr2phy_wrap
|
|
|
generic (
|
|
|
tech : integer := virtex2; MHz : integer := 100;
|
|
|
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
|
|
|
clk_mul : integer := 2; clk_div : integer := 2;
|
|
|
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
|
|
|
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
|
|
|
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
|
|
|
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
|
|
|
cbdelayb3 : integer := 0;
|
|
|
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
|
|
|
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
|
|
|
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
|
|
|
cben : integer := 0; chkbits : integer := 8; ctrl2en : integer := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkref200 : in std_logic; -- input 200MHz clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
|
|
|
ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits+padbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
|
|
|
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
|
|
|
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
|
|
|
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
|
|
|
ddr_web2 : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb2 : out std_ulogic; -- ddr ras
|
|
|
ddr_casb2 : out std_ulogic; -- ddr cas
|
|
|
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
|
|
|
sdi : out sdctrl_in_type;
|
|
|
sdo : in sdctrl_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ddr2phy_wrap_cbd is
|
|
|
generic (tech : integer := virtex2; MHz : integer := 100;
|
|
|
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
|
|
|
clk_mul : integer := 2 ; clk_div : integer := 2;
|
|
|
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
|
|
|
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
|
|
|
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
|
|
|
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
|
|
|
cbdelayb3 : integer := 0;
|
|
|
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
|
|
|
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
|
|
|
dqsse : integer range 0 to 1 := 0;
|
|
|
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
|
|
|
chkbits : integer := 0; ctrl2en : integer := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkref200 : in std_logic; -- input 200MHz clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
|
|
|
ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(ncs-1 downto 0);
|
|
|
|
|
|
ddr_web2 : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb2 : out std_ulogic; -- ddr ras
|
|
|
ddr_casb2 : out std_ulogic; -- ddr cas
|
|
|
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
|
|
|
sdi : out sdctrl_in_type;
|
|
|
sdo : in sdctrl_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component ftsrctrl8 is
|
|
|
generic (
|
|
|
hindex : integer := 0;
|
|
|
ramaddr : integer := 16#400#;
|
|
|
rammask : integer := 16#ff0#;
|
|
|
ioaddr : integer := 16#200#;
|
|
|
iomask : integer := 16#ff0#;
|
|
|
ramws : integer := 0;
|
|
|
iows : integer := 2;
|
|
|
srbanks : integer range 1 to 8 := 1;
|
|
|
banksz : integer range 0 to 15 := 15;
|
|
|
pindex : integer := 0;
|
|
|
paddr : integer := 0;
|
|
|
pmask : integer := 16#fff#;
|
|
|
edacen : integer range 0 to 1 := 1;
|
|
|
errcnt : integer range 0 to 1 := 1;
|
|
|
cntbits : integer range 1 to 8 := 1;
|
|
|
wsreg : integer := 0;
|
|
|
oepol : integer := 0
|
|
|
|
|
|
);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
apbi : in apb_slv_in_type;
|
|
|
apbo : out apb_slv_out_type;
|
|
|
sri : in memory_in_type;
|
|
|
sro : out memory_out_type
|
|
|
);
|
|
|
end component;
|
|
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type spimctrl_in_type is record
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miso : std_ulogic;
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mosi : std_ulogic;
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cd : std_ulogic;
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end record;
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type spimctrl_out_type is record
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mosi : std_ulogic;
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mosioen : std_ulogic;
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sck : std_ulogic;
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csn : std_ulogic;
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cdcsnoen : std_ulogic;
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errorn : std_ulogic;
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ready : std_ulogic;
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initialized : std_ulogic;
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end record;
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component spimctrl
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generic (
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hindex : integer := 0;
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hirq : integer := 0;
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faddr : integer := 16#000#;
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fmask : integer := 16#fff#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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spliten : integer := 0;
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oepol : integer := 0;
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sdcard : integer range 0 to 1 := 0;
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readcmd : integer range 0 to 255 := 16#0B#;
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dummybyte : integer range 0 to 1 := 1;
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dualoutput : integer range 0 to 1 := 0;
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scaler : integer range 1 to 512 := 1;
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altscaler : integer range 1 to 512 := 1;
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pwrupcnt : integer := 0;
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maxahbaccsz : integer range 0 to 256 := AHBDW
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);
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port (
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rstn : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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spii : in spimctrl_in_type;
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spio : out spimctrl_out_type
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);
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end component;
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end;
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