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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use std.textio.all;
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library lpp;
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use lpp.lpp_amba.all;
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use lpp.fft_components.all;
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--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
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package lpp_fft is
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component APB_FFT is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Data_sz : integer := 16
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);
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port (
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clk : in std_logic;
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rst : in std_logic; --! Reset general du composant
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type
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);
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end component;
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component APB_FFT_half is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Data_sz : integer := 16
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);
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port (
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clk : in std_logic; --! Horloge du composant
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rst : in std_logic; --! Reset general du composant
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Ren : in std_logic;
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ready : out std_logic;
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valid : out std_logic;
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DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
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DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
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OUTfill : out std_logic;
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OUTwrite : out std_logic;
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apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
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apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
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);
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end component;
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component FFT is
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generic(
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Data_sz : integer := 16;
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NbData : integer := 256);
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port(
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clkm : in std_logic;
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rstn : in std_logic;
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FifoIN_Empty : in std_logic_vector(4 downto 0);
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FifoIN_Data : in std_logic_vector(79 downto 0);
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FifoOUT_Full : in std_logic_vector(4 downto 0);
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Load : out std_logic;
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Read : out std_logic_vector(4 downto 0);
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Write : out std_logic_vector(4 downto 0);
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ReUse : out std_logic_vector(4 downto 0);
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Data : out std_logic_vector(79 downto 0)
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);
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end component;
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component Flag_Extremum is
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port(
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clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
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load : in std_logic; --! Signal en provenance de CoreFFT
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y_rdy : in std_logic; --! Signal en provenance de CoreFFT
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fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
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ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
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);
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end component;
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component Linker_FFT is
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generic(
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Data_sz : integer range 1 to 32 := 16;
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NbData : integer range 1 to 512 := 256
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);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Ready : in std_logic;
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Valid : in std_logic;
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Full : in std_logic_vector(4 downto 0);
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Data_re : in std_logic_vector(Data_sz-1 downto 0);
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Data_im : in std_logic_vector(Data_sz-1 downto 0);
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Read : out std_logic;
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Write : out std_logic_vector(4 downto 0);
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ReUse : out std_logic_vector(4 downto 0);
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DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
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);
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end component;
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component Driver_FFT is
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generic(
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Data_sz : integer range 1 to 32 := 16;
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NbData : integer range 1 to 512 := 256
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);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Load : in std_logic;
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Empty : in std_logic_vector(4 downto 0);
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DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
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Valid : out std_logic;
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Read : out std_logic_vector(4 downto 0);
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Data_re : out std_logic_vector(Data_sz-1 downto 0);
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Data_im : out std_logic_vector(Data_sz-1 downto 0)
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);
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end component;
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component FFTamont is
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generic(
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Data_sz : integer range 1 to 32 := 16;
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NbData : integer range 1 to 512 := 256
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);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Load : in std_logic;
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Empty : in std_logic;
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DATA : in std_logic_vector(Data_sz-1 downto 0);
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Valid : out std_logic;
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Read : out std_logic;
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Data_re : out std_logic_vector(Data_sz-1 downto 0);
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Data_im : out std_logic_vector(Data_sz-1 downto 0)
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);
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end component;
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component FFTaval is
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generic(
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Data_sz : integer range 1 to 32 := 8;
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NbData : integer range 1 to 512 := 256
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);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Ready : in std_logic;
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Valid : in std_logic;
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Full : in std_logic;
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Data_re : in std_logic_vector(Data_sz-1 downto 0);
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Data_im : in std_logic_vector(Data_sz-1 downto 0);
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Read : out std_logic;
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Write : out std_logic;
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ReUse : out std_logic;
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DATA : out std_logic_vector(Data_sz-1 downto 0)
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);
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end component;
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--==============================================================|
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--================== IP VHDL de la FFT actel ===================|
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--================ non partag� dans la VHD_Lib =================|
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--==============================================================|
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component CoreFFT IS
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GENERIC (
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LOGPTS : integer := gLOGPTS;
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LOGLOGPTS : integer := gLOGLOGPTS;
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WSIZE : integer := gWSIZE;
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TWIDTH : integer := gTWIDTH;
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DWIDTH : integer := gDWIDTH;
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TDWIDTH : integer := gTDWIDTH;
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RND_MODE : integer := gRND_MODE;
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SCALE_MODE : integer := gSCALE_MODE;
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PTS : integer := gPTS;
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HALFPTS : integer := gHALFPTS;
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inBuf_RWDLY : integer := gInBuf_RWDLY );
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PORT (
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clk,ifiStart,ifiNreset : IN std_logic;
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ifiD_valid, ifiRead_y : IN std_logic;
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ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
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ifoLoad, ifoPong : OUT std_logic;
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ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
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ifoY_valid, ifoY_rdy : OUT std_logic);
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END component;
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component actar is
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port( DataA : in std_logic_vector(15 downto 0); DataB : in
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std_logic_vector(15 downto 0); Mult : out
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std_logic_vector(31 downto 0);Clock : in std_logic) ;
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end component;
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component actram is
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port( DI : in std_logic_vector(31 downto 0); DO : out
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std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
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WADDR : in std_logic_vector(6 downto 0); RADDR : in
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std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
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std_logic) ;
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end component;
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component switch IS
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GENERIC ( DWIDTH : integer := 32 );
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PORT (
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clk, sel, validIn : IN std_logic;
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inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
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outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
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validOut : OUT std_logic);
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END component;
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component twid_rA IS
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GENERIC (LOGPTS : integer := 8;
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LOGLOGPTS : integer := 3 );
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PORT (clk : IN std_logic;
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timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
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stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
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tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
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END component;
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component counter IS
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GENERIC (
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WIDTH : integer := 7;
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TERMCOUNT : integer := 127 );
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PORT (
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clk, nGrst, rst, cntEn : IN std_logic;
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tc : OUT std_logic;
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Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
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END component;
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component twiddle IS
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PORT (
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A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
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T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
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END component;
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end;
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