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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: debug
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-- File: debug.vhd
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-- Author: Jiri Gaisler, Gaisler Research
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-- Description: Various debug utilities
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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package debug is
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component grtestmod
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generic (
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halt : integer := 0;
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width : integer := 32);
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port (
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resetn : in std_ulogic;
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clk : in std_ulogic;
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errorn : in std_ulogic;
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address : in std_logic_vector(21 downto 2);
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data : inout std_logic_vector(width-1 downto 0);
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iosn : in std_ulogic;
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oen : in std_ulogic;
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writen : in std_ulogic;
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brdyn : out std_ulogic;
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bexcn : out std_ulogic
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);
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end component;
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end;
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