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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: allclkgen
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-- File: allclkgen.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Clock generator interface package
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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package allclkgen is
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component clkgen_virtex2
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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noclkfb : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000;
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clk2xen : integer := 0;
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clksel : integer := 0); -- enable clock select
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port (
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clkin : in std_logic;
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pciclkin: in std_logic;
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clk : out std_logic; -- main clock
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clkn : out std_logic; -- inverted main clock
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clk2x : out std_logic; -- double clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type;
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clk1xu : out std_ulogic; -- unscaled clock
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clk2xu : out std_ulogic);
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end component;
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component clkgen_spartan3
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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noclkfb : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000;
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clk2xen : integer := 0;
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clksel : integer := 0); -- enable clock select
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port (
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clkin : in std_logic;
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pciclkin: in std_logic;
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clk : out std_logic; -- main clock
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clkn : out std_logic; -- inverted main clock
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clk2x : out std_logic; -- double clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type;
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clk1xu : out std_ulogic; -- unscaled clock
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clk2xu : out std_ulogic);
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end component;
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component clkgen_virtex5
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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noclkfb : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000;
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clk2xen : integer := 0;
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clksel : integer := 0); -- enable clock select
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port (
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clkin : in std_logic;
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pciclkin: in std_logic;
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clk : out std_logic; -- main clock
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clkn : out std_logic; -- inverted main clock
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clk2x : out std_logic; -- double clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type;
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clk1xu : out std_ulogic; -- unscaled clock
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clk2xu : out std_ulogic);
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end component;
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component clkgen_axcelerator
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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sdinvclk : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000);
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port (
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clkin : in std_logic;
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pciclkin: in std_logic;
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clk : out std_logic; -- main clock
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clkn : out std_logic; -- inverted main clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type);
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end component;
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component clkgen_altera_mf
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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sdinvclk : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000;
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clk2xen : integer := 0);
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port (
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clkin : in std_logic;
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pciclkin: in std_logic;
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clk : out std_logic; -- main clock
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clkn : out std_logic; -- inverted main clock
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clk2x : out std_logic; -- double clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type);
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end component;
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component clkgen_stratixii
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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sdinvclk : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000;
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clk2xen : integer := 0);
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port (
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clkin : in std_logic;
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pciclkin: in std_logic;
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clk : out std_logic; -- main clock
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clkn : out std_logic; -- inverted main clock
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clk2x : out std_logic; -- double clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type);
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end component;
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component clkgen_cycloneiii
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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sdinvclk : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000;
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clk2xen : integer := 0);
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port (
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clkin : in std_logic;
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pciclkin: in std_logic;
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clk : out std_logic; -- main clock
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clkn : out std_logic; -- inverted main clock
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clk2x : out std_logic; -- double clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type);
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end component;
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component clkgen_stratixiii
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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sdramen : integer := 0;
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sdinvclk : integer := 0;
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pcien : integer := 0;
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pcidll : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000;
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clk2xen : integer := 0);
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port (
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clkin : in std_logic;
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pciclkin: in std_logic;
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clk : out std_logic; -- main clock
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clkn : out std_logic; -- inverted main clock
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clk2x : out std_logic; -- double clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type);
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end component;
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component clkgen_rh_lib18t
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1);
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port (
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rst : in std_logic;
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clkin : in std_logic;
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clk : out std_logic;
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sdclk : out std_logic; -- SDRAM clock
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clk2x : out std_logic;
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clk4x : out std_logic
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);
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end component;
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component clkmul_virtex2
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generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
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port (
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resetin : in std_logic;
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clkin : in std_logic;
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clk : out std_logic;
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resetout: out std_logic
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);
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end component;
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component clkand_unisim
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port(
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i : in std_ulogic;
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en : in std_ulogic;
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o : out std_ulogic
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);
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end component;
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component clkand_ut025crh
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port(
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i : in std_ulogic;
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en : in std_ulogic;
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o : out std_ulogic
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);
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end component;
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component clkand_ut130hbd
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port(
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i : in std_ulogic;
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en : in std_ulogic;
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o : out std_ulogic;
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tsten : in std_ulogic
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);
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end component;
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component clkrand_ut130hbd
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port(
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i : in std_ulogic;
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en : in std_ulogic;
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o : out std_ulogic
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);
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end component;
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component clkand_rh_lib18t
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port(
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i : in std_ulogic;
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en : in std_ulogic;
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o : out std_ulogic;
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tsten : in std_ulogic
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);
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end component;
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component clkmux_unisim
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port(
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i0, i1 : in std_ulogic;
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sel : in std_ulogic;
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o : out std_ulogic
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);
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end component;
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component clkmux_ut130hbd
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port(
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i0, i1 : in std_ulogic;
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sel : in std_ulogic;
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o : out std_ulogic
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);
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end component;
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component clkmux_fusion
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port(
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i0, i1 : in std_ulogic;
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sel : in std_ulogic;
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o : out std_ulogic
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);
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end component;
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component altera_pll
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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clk_freq : integer := 25000;
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clk2xen : integer := 0;
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sdramen : integer := 0
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);
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port (
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inclk0 : in std_ulogic;
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c0 : out std_ulogic;
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c0_2x : out std_ulogic;
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e0 : out std_ulogic;
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locked : out std_ulogic);
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end component;
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component clkgen_proasic3
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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clk_odiv : integer := 1; -- output divider
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pcien : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000; -- clock frequency in KHz
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clkb_odiv: integer := 0;
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clkc_odiv: integer := 0);
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port (
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clkin : in std_ulogic;
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pciclkin: in std_ulogic;
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clk : out std_ulogic; -- main clock
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sdclk : out std_ulogic; -- SDRAM clock
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pciclk : out std_ulogic;
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type;
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clkb : out std_logic;
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clkc : out std_logic);
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end component;
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component clkgen_fusion
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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clk_odiv : integer := 1; -- output divider
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pcien : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000; -- clock frequency in KHz
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clkb_odiv: integer := 0;
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clkc_odiv: integer := 0);
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port (
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clkin : in std_ulogic;
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pciclkin: in std_ulogic;
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clk : out std_ulogic; -- main clock
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sdclk : out std_ulogic; -- SDRAM clock
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pciclk : out std_ulogic;
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type;
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clkb : out std_logic;
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clkc : out std_logic);
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end component;
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component clkgen_proasic3e
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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clk_odiv : integer := 1; -- output divider
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pcien : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000; -- clock frequency in KHz
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clkb_odiv: integer := 0;
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clkc_odiv: integer := 0);
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port (
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clkin : in std_ulogic;
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pciclkin: in std_ulogic;
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clk : out std_ulogic; -- main clock
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sdclk : out std_ulogic; -- SDRAM clock
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pciclk : out std_ulogic;
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type;
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clkb : out std_logic;
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clkc : out std_logic);
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end component;
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component clkgen_proasic3l
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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clk_odiv : integer := 1; -- output divider
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pcien : integer := 0;
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pcisysclk: integer := 0;
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freq : integer := 25000; -- clock frequency in KHz
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clkb_odiv: integer := 0;
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clkc_odiv: integer := 0);
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port (
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clkin : in std_ulogic;
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pciclkin: in std_ulogic;
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clk : out std_ulogic; -- main clock
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sdclk : out std_ulogic; -- SDRAM clock
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pciclk : out std_ulogic;
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type;
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clkb : out std_logic;
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clkc : out std_logic);
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end component;
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component cyclone3_pll is
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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clk_freq : integer := 25000;
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clk2xen : integer := 0;
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sdramen : integer := 0
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);
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port (
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inclk0 : in std_ulogic;
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c0 : out std_ulogic;
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c0_2x : out std_ulogic;
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e0 : out std_ulogic;
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locked : out std_ulogic);
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end component;
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|
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component stratix3_pll
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generic (
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clk_mul : integer := 1;
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clk_div : integer := 1;
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clk_freq : integer := 25000;
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clk2xen : integer := 0;
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sdramen : integer := 0
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);
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port (
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inclk0 : in std_ulogic;
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c0 : out std_ulogic;
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c0_2x : out std_ulogic;
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e0 : out std_ulogic;
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locked : out std_ulogic);
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end component;
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component clkgen_dare
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port (
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clkin : in std_logic;
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clk : out std_logic; -- main clock
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clk2x : out std_logic; -- 2x clock
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sdclk : out std_logic; -- SDRAM clock
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pciclk : out std_logic; -- PCI clock
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cgi : in clkgen_in_type;
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cgo : out clkgen_out_type;
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clk4x : out std_logic; -- 4x clock
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clk1xu : out std_logic; -- unscaled 1X clock
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clk2xu : out std_logic); -- unscaled 2X clock
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end component;
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component clkgen_easic90
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generic (
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clk_mul : integer;
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clk_div : integer;
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freq : integer;
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pcisysclk : integer;
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|
pcien : integer);
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port (
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clkin : in std_ulogic;
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pciclkin : in std_ulogic;
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clk : out std_ulogic;
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clk2x : out std_ulogic;
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clk4x : out std_ulogic;
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clkn : out std_ulogic;
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lock : out std_ulogic);
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end component;
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component clkmux_rhlib18t
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port(
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i0 : in std_ulogic;
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i1 : in std_ulogic;
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sel : in std_ulogic;
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|
o : out std_ulogic);
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|
end component;
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component clkand_n2x
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|
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port(
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i : in std_ulogic;
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en : in std_ulogic;
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|
o : out std_ulogic;
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|
|
tsten : in std_ulogic := '0'
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|
);
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|
end component;
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|
|
component clkgen_n2x
|
|
|
generic (
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|
clk_mul : integer := 1;
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|
|
clk_div : integer := 1;
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|
|
sdramen : integer := 0;
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|
|
noclkfb : integer := 0;
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|
|
pcien : integer := 0;
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|
|
pcidll : integer := 0;
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|
|
pcisysclk: integer := 0;
|
|
|
freq : integer := 25000; -- clock frequency in KHz
|
|
|
clk2xen : integer := 0;
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|
|
clksel : integer := 0; -- enable clock select
|
|
|
clk270en : integer := 0);
|
|
|
port (
|
|
|
clkin : in std_ulogic;
|
|
|
pciclkin: in std_ulogic;
|
|
|
clk : out std_ulogic; -- main clock
|
|
|
clkn : out std_ulogic; -- inverted main clock
|
|
|
clk2x : out std_ulogic; -- double clock
|
|
|
sdclk : out std_ulogic; -- SDRAM clock
|
|
|
pciclk : out std_ulogic; -- PCI clock
|
|
|
cgi : in clkgen_in_type;
|
|
|
cgo : out clkgen_out_type;
|
|
|
clk1xu : out std_ulogic; -- unscaled clock
|
|
|
clk2xu : out std_ulogic; -- unscaled 2X clock
|
|
|
clk270 : out std_ulogic -- clk shifted 270 degrees
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component clkgen_ut130hbd
|
|
|
generic (
|
|
|
clk_mul : integer := 1;
|
|
|
clk_div : integer := 1;
|
|
|
sdramen : integer := 0;
|
|
|
noclkfb : integer := 0;
|
|
|
pcien : integer := 0;
|
|
|
pcidll : integer := 0;
|
|
|
pcisysclk: integer := 0;
|
|
|
freq : integer := 25000; -- clock frequency in KHz
|
|
|
clk2xen : integer := 0;
|
|
|
clksel : integer := 0); -- enable clock select
|
|
|
port (
|
|
|
clkin : in std_ulogic;
|
|
|
pciclkin: in std_ulogic;
|
|
|
clk : out std_ulogic; -- main clock
|
|
|
clkn : out std_ulogic; -- inverted main clock
|
|
|
clk2x : out std_ulogic; -- double clock
|
|
|
sdclk : out std_ulogic; -- SDRAM clock
|
|
|
pciclk : out std_ulogic; -- PCI clock
|
|
|
cgi : in clkgen_in_type;
|
|
|
cgo : out clkgen_out_type;
|
|
|
clk1xu : out std_ulogic; -- unscaled clock
|
|
|
clk2xu : out std_ulogic -- unscaled 2X clock
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component clkgen_ut90nhbd is
|
|
|
generic (
|
|
|
clk_mul : integer := 1;
|
|
|
clk_div : integer := 1;
|
|
|
sdramen : integer := 0;
|
|
|
noclkfb : integer := 0;
|
|
|
pcien : integer := 0;
|
|
|
pcidll : integer := 0;
|
|
|
pcisysclk: integer := 0;
|
|
|
freq : integer := 25000; -- clock frequency in KHz
|
|
|
clk2xen : integer := 0;
|
|
|
clksel : integer := 0); -- enable clock select
|
|
|
port (
|
|
|
clkin : in std_ulogic;
|
|
|
pciclkin: in std_ulogic;
|
|
|
clk : out std_ulogic; -- main clock
|
|
|
clkn : out std_ulogic; -- inverted main clock
|
|
|
clk2x : out std_ulogic; -- double clock
|
|
|
sdclk : out std_ulogic; -- SDRAM clock
|
|
|
pciclk : out std_ulogic; -- PCI clock
|
|
|
cgi : in clkgen_in_type;
|
|
|
cgo : out clkgen_out_type;
|
|
|
clk1xu : out std_ulogic; -- unscaled clock
|
|
|
clk2xu : out std_ulogic -- unscaled 2X clock
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
end;
|
|
|
|