KEY LIBERO "8.6"
KEY CAPTURE "8.6.2.10"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "Virtex2"
KEY VendorTechnology_Die ""
KEY VendorTechnology_Package ""
KEY ProjectLocation "."
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "leon3mp"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
grlib
secureip
eclipsee
synplify
techmap
spw
eth
opencores
core1553bbc
core1553brt
core1553brm
corePCIF
gaisler
esa
gleichmann
fmf
spansion
gsi
lpp
cypress
hynix
micron
openchip
work
ENDLIST
LIST LIBRARIES_grlib
ALIAS=grlib
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_secureip
ALIAS=secureip
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_eclipsee
ALIAS=eclipsee
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_synplify
ALIAS=synplify
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_techmap
ALIAS=techmap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_spw
ALIAS=spw
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_eth
ALIAS=eth
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_opencores
ALIAS=opencores
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_core1553bbc
ALIAS=core1553bbc
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_core1553brt
ALIAS=core1553brt
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_core1553brm
ALIAS=core1553brm
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_corePCIF
ALIAS=corePCIF
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gaisler
ALIAS=gaisler
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_esa
ALIAS=esa
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gleichmann
ALIAS=gleichmann
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_fmf
ALIAS=fmf
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_spansion
ALIAS=spansion
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gsi
ALIAS=gsi
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_lpp
ALIAS=lpp
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_cypress
ALIAS=cypress
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_hynix
ALIAS=hynix
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_micron
ALIAS=micron
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_openchip
ALIAS=openchip
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_work
ALIAS=work
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
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VALUE "<project>/../../lib/grlib/sparc/sparc_disas.vhd,hdl"
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VALUE "<project>/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/ApbDriver.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_uart/UART.vhd,hdl"
VALUE "<project>/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"
VALUE "<project>/../../lib/cypress/ssram/components.vhd,hdl"
VALUE "<project>/../../lib/cypress/ssram/package_utility.vhd,hdl"
VALUE "<project>/../../lib/cypress/ssram/cy7c1354b.vhd,hdl"
VALUE "<project>/../../lib/cypress/ssram/cy7c1380d.vhd,hdl"
VALUE "<project>/../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd,hdl"
VALUE "<project>/../../lib/hynix/ddr2/HY5PS121621F.vhd,hdl"
VALUE "<project>/../../lib/hynix/ddr2/components.vhd,hdl"
VALUE "<project>/../../lib/micron/sdram/mobile_sdr.v,hdl"
VALUE "<project>/../../lib/micron/sdram/components.vhd,hdl"
VALUE "<project>/../../lib/micron/sdram/mt48lc16m16a2.vhd,hdl"
VALUE "<project>/../../lib/micron/ddr/ddr2.v,hdl"
VALUE "<project>/../../lib/micron/ddr/mobile_ddr.v,hdl"
VALUE "<project>/../../lib/micron/ddr/ddr3.v,hdl"
VALUE "<project>/../../lib/micron/ddr/mt46v16m16.vhd,hdl"
VALUE "<project>/../../lib/openchip/gpio/gpio.vhd,hdl"
VALUE "<project>/../../lib/openchip/gpio/apbgpio.vhd,hdl"
VALUE "<project>/../../lib/openchip/charlcd/charlcd.vhd,hdl"
VALUE "<project>/../../lib/openchip/charlcd/apbcharlcd.vhd,hdl"
VALUE "<project>/../../lib/openchip/sui/sui.vhd,hdl"
VALUE "<project>/../../lib/openchip/sui/apbsui.vhd,hdl"
VALUE "<project>/../../lib/work/debug/debug.vhd,hdl"
VALUE "<project>/../../lib/work/debug/grtestmod.vhd,hdl"
VALUE "<project>/../../lib/work/debug/cpu_disas.vhd,hdl"
VALUE "<project>/config.vhd,hdl"
VALUE "<project>/ahbrom.vhd,hdl"
VALUE "<project>/leon3mp.vhd,hdl"
ENDFILELIST
ENDLIST
ENDLIST
ENDLIST