xilinx.com project mig 1.0 mig_392 mig_392 ./mig.prj mig ./ ./tmp/ ./tmp/_cg/ xc6slx45t spartan6 fgg484 -3 BusFormatParenNotRipped VHDL true Synplicity false false false Ngc false Behavioral VHDL false mig_38 mig_38 ./mig_38/user_design/mig.prj mig ./ ./tmp/ ./tmp/_cg/ xc6slx45 spartan6 fgg484 -3 BusFormatAngleBracketNotRipped VHDL true Other false false false Ngc false Behavioral VHDL false 2012-07-21+06:31 apply_current_project_options_generator customization_generator ./mig_38/docs/ug388.pdf ignore pdf Mon Apr 08 17:56:55 GMT 2013 0x90FCF0D1 generationID_4013899584 ./mig_38/docs/ug416.pdf ignore pdf Mon Apr 08 17:56:55 GMT 2013 0x5A2D5D89 generationID_4013899584 ./mig_38/example_design/datasheet.txt ignore txt Mon Apr 08 17:56:55 GMT 2013 0x3B3D8F7B generationID_4013899584 ./mig_38/example_design/mig.prj ignore unknown Mon Apr 08 17:56:55 GMT 2013 0x74598905 generationID_4013899584 ./mig_38/example_design/par/create_ise.sh ignore unknown Mon Apr 08 17:56:55 GMT 2013 0x2E26C0EA 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mig ./ ./tmp/ ./tmp/_cg/ xc6slx45 spartan6 fgg484 -3 BusFormatAngleBracketNotRipped VHDL true Other false false false Ngc false Behavioral VHDL false