KEY LIBERO "8.1"
KEY CAPTURE "8.1.0.32"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "PROASIC3"
KEY VendorTechnology_Die "IT14X14M4LDP"
KEY VendorTechnology_Package "fg484"
KEY ProjectLocation "."
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "leon3mp"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
grlib
proasic3
synplify
techmap
spw
eth
opencores
gaisler
esa
fmf
spansion
gsi
lpp
cypress
work
ENDLIST
LIST LIBRARIES_grlib
ALIAS=grlib
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_proasic3
ALIAS=proasic3
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_synplify
ALIAS=synplify
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_techmap
ALIAS=techmap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_spw
ALIAS=spw
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_eth
ALIAS=eth
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_opencores
ALIAS=opencores
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gaisler
ALIAS=gaisler
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_esa
ALIAS=esa
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_fmf
ALIAS=fmf
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_spansion
ALIAS=spansion
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gsi
ALIAS=gsi
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_lpp
ALIAS=lpp
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_cypress
ALIAS=cypress
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_work
ALIAS=work
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
VALUE "<project>/../..//lib/grlib/stdlib/version.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/stdlib/stdlib.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/stdlib/stdio.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/util/util.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/sparc/sparc.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/sparc/sparc_disas.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/sparc/cpu_disas.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/modgen/multlib.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/modgen/leaves.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/amba.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/devices.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/defmst.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/apbctrl.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/ahbctrl.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/dma2ahb_pkg.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/dma2ahb.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/dma2ahb_tp.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/tech/proasic3/components/proasic3.vhd,hdl"
STATE="utd"
LIBRARY="proasic3"
ENDFILE
VALUE "<project>/../..//lib/synplify/sim/synplify.vhd,hdl"
STATE="utd"
LIBRARY="synplify"
ENDFILE
VALUE "<project>/../..//lib/synplify/sim/synattr.vhd,hdl"
STATE="utd"
LIBRARY="synplify"
ENDFILE
VALUE "<project>/../..//lib/techmap/gencomp/gencomp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/gencomp/netcomp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/inferred/memory_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/inferred/ddr_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/inferred/mul_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/proasic3/memory_apa3.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/proasic3/buffer_apa3.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/proasic3/tap_proasic3.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/allclkgen.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/allddr.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/allmem.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/allpads.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/alltap.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkgen.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkmux.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkand.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ddr_ireg.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ddr_oreg.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ddrphy.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncram.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncram64.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncram_2p.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncram_dp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncfifo.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/regfile_3p.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/tap.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/techbuf.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/inpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/inpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/iodpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/iopad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/iopad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/lvds_combo.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/odpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/outpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/outpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/toutpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/skew_outpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/grspwc_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/grlfpw_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/grfpw_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/mul_61x61.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/cpu_disas_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/usbhc_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ringosc.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ssrctrl_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/spw/comp/spwcomp.vhd,hdl"
STATE="utd"
LIBRARY="spw"
ENDFILE
VALUE "<project>/../..//lib/eth/comp/ethcomp.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/greth_pkg.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/eth_rstgen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/eth_ahb_mst.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/greth_tx.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/greth_rx.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/grethc.vhd,hdl"
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LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/wrapper/greth_gen.vhd,hdl"
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LIBRARY="eth"
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VALUE "<project>/../..//lib/eth/wrapper/greth_gbit_gen.vhd,hdl"
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LIBRARY="eth"
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VALUE "<project>/../..//lib/opencores/occomp/occomp.vhd,hdl"
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ENDFILELIST
ENDLIST
ENDLIST
ENDLIST