HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Changelog

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HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib

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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

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	`r223:006079fa8bed`	Added cross domain synchronisation blocks.	Thu, 22 Aug 2013 23:55:11	jeandet	alexis	0
	`r222:b37e19fe4c0b`	Fixed bug, now minor and major frame pulses have the good width. (one sck period and not one word clock period)	Thu, 15 Aug 2013 13:23:49	Alexis Jeandet	alexis	0
	`r221:61667259e0ed`	Sync	Wed, 14 Aug 2013 12:27:02	Alexis Jeandet	alexis	0
	`r220:9cd9574d2765`	ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen. Solved in place design developpment problem on Windows, look at EGSE_ICI makefile.	Tue, 13 Aug 2013 09:30:57	Alexis Jeandet	alexis	0
	`r219:df1aff8cd31b`	ICI4 EGSE now working, need some more cleaning.	Mon, 12 Aug 2013 21:39:34	Alexis Jeandet	alexis	0
	`r218:8124d5736ed6`	Cleaned EGSE_ICI design.	Tue, 06 Aug 2013 06:19:55	Alexis Jeandet	alexis	0
	`r217:13429b36c676`	Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.	Mon, 05 Aug 2013 19:45:52	Alexis Jeandet	alexis	0
	`r216:f6be3dc03b2a`	Fusion avec JC	Mon, 05 Aug 2013 08:31:07	Alexis Jeandet	merge alexis	0
	`r181:2a5b3fda6e52`	Sync	Tue, 21 May 2013 09:05:02	Alexis Jeandet	alexis	0
	`r168:0b190be76d60`	ICI rockets designs added	Thu, 02 May 2013 16:29:53	jeandet	alexis	0
	`r136:217245b6ebff`	fixed mistake on linklibs.sh script.	Fri, 12 Apr 2013 10:41:47	jeandet	alexis	0
	`r135:0c6f64b8ccc5`	sync	Fri, 12 Apr 2013 09:25:29	jeandet	alexis	0
	`r134:aecffb18871a`	Fusion avec JC	Fri, 12 Apr 2013 08:18:33	jeandet	merge alexis	0
	`r129:8459a437c1f1`	Added ICI4 designs. Added link option to install VHDlid, make link will just link vhdlib to grlib without any need to copy it.	Wed, 10 Apr 2013 21:26:23	jeandet	alexis	0
	`r128:2cf6488c258b`	temp	Mon, 08 Apr 2013 17:14:29	jeandet	alexis	0
	`r92:74ac16764d41`	IIR Filter Ready for tests, New version of APB_FIFO under developpement.	Wed, 11 Jan 2012 12:06:00	jeandet@PC-DE-JEANDET.lpp.polytechnique.fr	alexis	0
	`r89:ca0a305588e9`	Removed reference to ssram_plugin2.	Mon, 05 Dec 2011 12:07:08	jeandet@PC-DE-JEANDET.lpp.polytechnique.fr	alexis	0
	`r88:e9b46526a70d`	SSRAM_plugin.vhd now working! SRAM need clk 2x faster than AHB bus! Added LFR-BBM board and design.	Mon, 05 Dec 2011 08:54:15	jeandet@PC-DE-JEANDET.lpp.polytechnique.fr	alexis	0
	`r85:439b6d5bebcc`	/!\ Unstable LFR-142200-DM-LEON3-BASE design /!\	Fri, 04 Nov 2011 14:57:41	jeandet@PC-DE-JEANDET.lpp.polytechnique.fr	alexis	0
	`r84:6c2ce1d3393f`	Added SSRAM plugin for LFR developpement model	Tue, 18 Oct 2011 06:45:46	jeandet@PC-DE-JEANDET.lpp.polytechnique.fr	alexis	0
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